Hybrid Bonding on KAD

SK Hynix Targets 20+ Layer HBM5 Stacks With Hybrid Bonding

Sun, 13 Sep 2026 12:10:05 +0800

SK Hynix Targets 20+ Layer HBM5 Stacks With Hybrid Bonding

SK Hynix has outlined its next-generation high-bandwidth memory packaging roadmap, showing how HBM could scale beyond the current 16-layer ceiling while remaining within the physical constraints of advanced AI accelerator packages.

Huawei Tau Scaling: How LogicFolding Targets Chip Power and Heat

Sat, 05 Sep 2026 18:38:56 +0800

Huawei Tau Scaling: How LogicFolding Targets Chip Power and Heat

Huawei semiconductor executive He Tingbo has published a new paper addressing one of the most obvious challenges surrounding the company’s proposed Tau (τ) scaling law: thermal management.

Samsung 900-Layer NAND: 450-Layer Wafer Bonding Explained

Fri, 28 Aug 2026 23:08:39 +0800

Samsung 900-Layer NAND: 450-Layer Wafer Bonding Explained

Samsung has developed a prototype 900-layer 3D NAND flash chip using its proprietary Cell Multi-Bonding (CMB) technology, marking a major shift in how NAND manufacturers can scale vertical memory density.

Samsung and SK hynix Delay Hybrid Bonding for HBM4 as Memory Roadmaps Shift

Tue, 07 Jul 2026 18:25:32 +0800

Samsung and SK hynix Delay Hybrid Bonding for HBM4 as Memory Roadmaps Shift

Hybrid bonding, long expected to become one of the defining technologies of the HBM4 generation, is reportedly being pushed further down the roadmap by both Samsung and SK hynix. Instead of debuting with HBM4, the advanced packaging technology is now expected to arrive with later generations such as HBM4E or HBM5E.