<?xml version="1.0" encoding="utf-8" standalone="yes"?>
<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom">
  <channel>
    <title>LLM Infrastructure on KAD</title>
    <link>https://www.kad8.com/tags/llm-infrastructure/</link>
    <description>Recent content in LLM Infrastructure on KAD</description>
    <generator>Hugo -- gohugo.io</generator>
    <language>en</language>
    <copyright>© 2026 </copyright>
    <lastBuildDate>Tue, 22 Sep 2026 18:13:02 +0800</lastBuildDate><atom:link href="https://www.kad8.com/tags/llm-infrastructure/index.xml" rel="self" type="application/rss+xml" />
    <item>
      <title>Understanding CXL Part 2: System Networking and Memory Ecosystem</title>
      <link>https://www.kad8.com/hardware/understanding-cxl-part-2-system-networking-and-memory-ecosystem/</link>
      <pubDate>Tue, 22 Sep 2026 18:13:02 +0800</pubDate>
      
      <guid>https://www.kad8.com/hardware/understanding-cxl-part-2-system-networking-and-memory-ecosystem/</guid>
      <description>&lt;blockquote&gt;
&lt;p&gt;Understanding CXL Part 2: System Networking and Memory Ecosystem&lt;/p&gt;&lt;/blockquote&gt;
&lt;p&gt;&lt;strong&gt;📋 Summary:&lt;/strong&gt; Compute Express Link (CXL) has evolved from a direct CPU-to-memory expansion interface into a broader system-level interconnect technology. CXL 1.1 focused on single-host memory expansion, CXL 2.0 introduced switching and memory pooling, while CXL 3.x expands the architecture toward multi-host coherency and large-scale fabric networking. This article examines that evolution, the CXL product ecosystem, memory-vendor strategies, controller and switch silicon, and the practical limitations of CXL deployment.&lt;/p&gt;</description>
      <media:content xmlns:media="http://search.yahoo.com/mrss/" url="https://www.kad8.com/hardware/understanding-cxl-part-2-system-networking-and-memory-ecosystem/featured-Compute_Express_Link_evolution.jpeg" />
    </item>
    
    <item>
      <title>AWS Explores Qualcomm AI200 Chips with 768GB Memory for AI Inference</title>
      <link>https://www.kad8.com/ai/aws-explores-qualcomm-ai200-chips-with-768gb-memory-for-ai-inference/</link>
      <pubDate>Sat, 13 Jun 2026 22:57:19 +0800</pubDate>
      
      <guid>https://www.kad8.com/ai/aws-explores-qualcomm-ai200-chips-with-768gb-memory-for-ai-inference/</guid>
      <description>&lt;blockquote&gt;
&lt;p&gt;AWS Explores Qualcomm AI200 Chips with 768GB Memory for AI Inference&lt;/p&gt;&lt;/blockquote&gt;


&lt;h2 class=&#34;relative group&#34;&gt;☁️ Hyperscale AI Infrastructure Enters a Memory-Centric Phase 
    &lt;div id=&#34;-hyperscale-ai-infrastructure-enters-a-memory-centric-phase&#34; class=&#34;anchor&#34;&gt;&lt;/div&gt;
    
    &lt;span
        class=&#34;absolute top-0 w-6 transition-opacity opacity-0 ltr:-left-6 rtl:-right-6 not-prose group-hover:opacity-100&#34;&gt;
        &lt;a class=&#34;group-hover:text-primary-300 dark:group-hover:text-neutral-700&#34;
            style=&#34;text-decoration-line: none !important;&#34; href=&#34;#-hyperscale-ai-infrastructure-enters-a-memory-centric-phase&#34; aria-label=&#34;Anchor&#34;&gt;#&lt;/a&gt;
    &lt;/span&gt;        
    
&lt;/h2&gt;
&lt;p&gt;A recent industry report attributed to Wells Fargo suggests that AWS may become a key hyperscale partner for Qualcomm’s AI200 inference accelerator, a chip reportedly designed with an unusually large &lt;strong&gt;768GB of on-package memory per processor&lt;/strong&gt;. The move reflects a broader shift in cloud computing toward optimizing inference efficiency rather than raw training throughput.&lt;/p&gt;</description>
      <media:content xmlns:media="http://search.yahoo.com/mrss/" url="https://www.kad8.com/ai/aws-explores-qualcomm-ai200-chips-with-768gb-memory-for-ai-inference/featured-AWS_adopts_Qualcomm_AI_chips.jpeg" />
    </item>
    
  </channel>
</rss>
