AI Accelerator Interconnects: PCIe, NVLink, CXL, UALink and UCIe

AI Accelerator Interconnects: PCIe, NVLink, CXL, UALink and UCIe

Modern AI infrastructure depends on far more than raw accelerator compute. GPUs, CPUs, memory devices, and chiplets must exchange enormous amounts of data with minimal latency and overhead. As AI models become larger and accelerator clusters grow, the interconnect increasingly determines how effectively available compute can be used.

Technologies such as PCIe, NVIDIA NVLink, CXL, AMD Infinity Fabric, UALink, and UCIe address different parts of this communication problem. Some connect devices across a server, others create high-bandwidth accelerator fabrics, while UCIe targets communication between chiplets inside a package.

Understanding these technologies provides a useful foundation for evaluating modern AI servers, HPC systems, and next-generation heterogeneous computing architectures.

⚡ Why Interconnects Matter for AI

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AI accelerators can perform enormous numbers of calculations per second, but computation is only useful when data can reach the processing units quickly enough.

Large training and inference workloads continuously move:

• Model parameters
• Activations
• Gradients
• Training datasets
• Intermediate tensors
• Memory-management metadata
• Synchronization information

An interconnect therefore affects much more than simple device-to-device transfers. Its bandwidth, latency, topology, coherency model, scalability, and power efficiency can determine whether a large accelerator system operates near its theoretical performance.

The major technologies can be summarized as follows:

These technologies are complementary rather than interchangeable.

🖥️ PCIe: The Universal Accelerator Interface

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PCIe remains the fundamental high-speed expansion interface for modern computing platforms.

GPUs, AI accelerators, network adapters, storage controllers, and other peripherals commonly connect to CPUs and host systems through PCIe.

Key Characteristics

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PCIe provides several properties that make it an important foundation for AI infrastructure:

• High bandwidth through scalable lane configurations
• Full-duplex communication for simultaneous transmission and reception
• Point-to-point connectivity between devices and switches
• Backward compatibility across generations
• Broad ecosystem support
• Hot-plug capabilities in supported platforms

PCIe 5.0 provides 32 GT/s per lane, while PCIe 6.0 doubles that signaling rate to 64 GT/s. PCIe 7.0 targets 128 GT/s per lane.

For a x16 connection, the theoretical raw signaling rate scales dramatically with each generation, although protocol overhead means usable application bandwidth is lower than the headline transfer rate.

PCIe’s Role in AI Systems

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PCIe is particularly important as the host-facing interface for accelerators.

A typical AI server may use PCIe to connect:

• CPUs to GPUs
• CPUs to AI accelerators
• CPUs to NICs
• Accelerators to storage
• Accelerators to PCIe switches

However, PCIe is not necessarily optimized for tightly coupled communication among dozens or hundreds of accelerators. This is where specialized accelerator fabrics become important.

🚀 NVLink and NVSwitch: NVIDIA’s Accelerator Fabric

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NVLink is NVIDIA’s proprietary high-bandwidth interconnect designed primarily for communication between GPUs and other NVIDIA compute components.

Unlike conventional PCIe attachment, NVLink is optimized for the intensive communication patterns generated by large-scale accelerator workloads.

High Bandwidth and Low Latency

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NVLink provides substantially greater bandwidth than conventional PCIe connections in systems designed around the technology.

Direct high-speed links allow GPUs to exchange data without always routing traffic through the CPU or system memory.

This is particularly valuable for:

• Distributed AI training
• Large-model inference
• Tensor-parallel workloads
• Collective communication
• GPU memory sharing
• Accelerator synchronization

NVSwitch and Scale-Out GPU Fabrics

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NVSwitch extends the NVLink concept from point-to-point connections into a switched fabric.

Instead of creating a simple chain or collection of isolated GPU pairs, NVSwitch enables many accelerators to communicate through a high-bandwidth switching infrastructure.

This makes it possible to build large GPU systems in which accelerator-to-accelerator communication becomes a fundamental part of the architecture rather than an afterthought.

The result is an ecosystem optimized around NVIDIA’s accelerator platform, with NVLink providing the communication layer and NVSwitch providing scalable connectivity.

🧠 CXL: Bringing Coherency to Heterogeneous Computing

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Compute Express Link (CXL) takes a different approach.

Rather than focusing exclusively on GPU-to-GPU communication, CXL extends the PCIe physical infrastructure with protocols designed for coherent communication among CPUs, accelerators, and memory devices.

The Three Core CXL Protocols

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CXL is generally described through three major protocol types:

• CXL.io — Provides conventional device discovery, configuration, and I/O semantics.
• CXL.cache — Allows devices such as accelerators to access host memory coherently.
• CXL.mem — Enables processors to access memory attached to CXL devices.

This combination allows system designers to construct more flexible heterogeneous memory and compute architectures.

Breaking the Traditional Memory Model

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Traditional server architectures often treat each accelerator and memory subsystem as relatively separate resources.

CXL enables a more coordinated model in which CPUs, accelerators, and memory expansion devices can participate in a coherent system.

Potential applications include:

• Memory expansion
• Memory pooling
• Accelerator attachment
• Tiered memory
• Resource disaggregation
• Heterogeneous computing

For AI infrastructure, CXL is particularly interesting because increasing model sizes place enormous pressure on memory capacity and bandwidth.

🔷 AMD Infinity Fabric: Scalable Communication Across Dies

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AMD’s Infinity Fabric is a scalable interconnect architecture used throughout AMD’s processor and accelerator ecosystem.

It connects computing elements both within individual packages and across larger systems.

Infinity Fabric plays an important role in architectures involving:

• EPYC processors
• Instinct accelerators
• Multi-die processors
• Chiplets
• High-performance memory subsystems

Chiplet-Oriented Scaling

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AMD’s extensive use of chiplets makes efficient die-to-die communication essential.

Instead of placing every processing element on one enormous monolithic die, modern AMD processors can combine multiple compute dies and supporting components within a package.

Infinity Fabric provides the communication infrastructure needed to coordinate these components.

The same architectural philosophy extends into AMD’s AI accelerator platforms, where multiple compute and memory components must operate as a coordinated system.

🌐 UALink: An Open Approach to Accelerator Connectivity

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Ultra Accelerator Link (UALink) is an industry initiative aimed at creating an open standard for connecting AI accelerators.

The motivation is straightforward: as AI clusters become larger, relying on a single proprietary accelerator interconnect can constrain hardware choices and system interoperability.

UALink is designed to provide scalable accelerator-to-accelerator communication while supporting a broader multi-vendor ecosystem.

Key Objectives

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The technology targets capabilities such as:

• High-bandwidth accelerator communication
• Shared-memory-style semantics
• Scalable accelerator topologies
• Multi-vendor interoperability
• Large accelerator pools

UALink is particularly relevant to hyperscale AI infrastructure, where operators may want to combine components from multiple vendors rather than building an entire system around one proprietary fabric.

UALink vs. NVLink

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The distinction is largely architectural and ecosystem-oriented.

NVLink is a mature proprietary technology tightly integrated with NVIDIA’s accelerator platform.

UALink aims to establish an open industry standard that can be adopted across different accelerator and system vendors.

This makes UALink potentially important for organizations seeking greater hardware interoperability and vendor diversity.

🧩 UCIe: The Interconnect for Chiplet-Based Designs

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Universal Chiplet Interconnect Express (UCIe) addresses a different level of the computing hierarchy.

While PCIe, NVLink, CXL, and UALink primarily concern communication between larger system components, UCIe focuses on die-to-die communication between chiplets.

Modern processors increasingly use multiple smaller dies instead of a single monolithic piece of silicon. This can improve manufacturing yield, allow specialized process nodes, and make it possible to combine components from different IP providers.

UCIe provides a standardized framework for connecting those chiplets.

A Standardized Chiplet Interface

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UCIe defines important aspects of chiplet communication, including:

• Physical-layer connectivity
• Die-to-die protocols
• Protocol adaptation
• Software-related interoperability
• Reliability and integrity mechanisms

The standard can support established protocols such as PCIe and CXL while providing a foundation for future chiplet-based architectures.

Why UCIe Matters for AI

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AI accelerators increasingly combine different types of silicon:

• Compute dies
• I/O dies
• Memory controllers
• Cache components
• Specialized accelerators
• Networking logic

A standardized chiplet interface could make it easier to construct these systems from modular components.

Instead of designing one enormous monolithic accelerator, manufacturers can potentially combine specialized chiplets into a larger heterogeneous package.

🔄 How These Interconnects Fit Together

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It is useful to think of these technologies as operating at different architectural levels.

A future AI server could potentially use several of them simultaneously.

For example:

                 AI SERVER
                     │
              ┌──────┴──────┐
              │     CPU     │
              └──────┬──────┘
                     │
                  PCIe / CXL
                     │
          ┌──────────┴──────────┐
          │                     │
      AI Accelerator        Memory Device
          │                     │
      Accelerator Fabric       CXL
          │
   ┌──────┼──────┐
   │      │      │
 GPU/AI  GPU/AI  GPU/AI
   │
 UCIe / Die-to-Die
   │
┌──┴───────────────┐
│ Compute Chiplets │
│ I/O Chiplets     │
│ Cache / Control  │
└──────────────────┘

The exact implementation varies by vendor, but the underlying concept is important: modern AI systems are becoming hierarchical interconnect networks rather than collections of isolated processors.

📊 Comparing the Major AI Interconnects

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No single interconnect solves every problem.

PCIe excels at general-purpose connectivity. NVLink focuses on tightly coupled NVIDIA accelerator systems. CXL introduces coherency and memory expansion capabilities. Infinity Fabric provides AMD’s scalable internal architecture. UALink targets open accelerator fabrics, while UCIe addresses the rapidly growing chiplet ecosystem.

⚡ Bandwidth Is Only Part of the Equation

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It is tempting to compare interconnects solely by their headline bandwidth, but that can be misleading.

Real-world accelerator performance also depends on:

• Latency
• Protocol overhead
• Memory access semantics
• Topology
• Collective communication efficiency
• Software support
• Switching architecture
• Power consumption
• Error handling
• Coherency mechanisms
• Number of connected devices

A theoretically faster link can provide little practical advantage if the workload cannot efficiently exploit its bandwidth.

For large AI models, the architecture of the entire communication fabric can therefore matter as much as the raw link speed.

🏗️ The Future of AI Interconnects

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AI infrastructure is moving toward increasingly heterogeneous architectures.

Future systems are likely to combine:

• CPUs
• GPUs
• Dedicated AI accelerators
• High-bandwidth memory
• CXL memory pools
• Chiplet-based processors
• High-speed networking
• Specialized accelerator fabrics

This evolution creates pressure for both higher bandwidth and greater interoperability.

At the package level, UCIe can help connect heterogeneous chiplets. At the server level, PCIe and CXL provide standardized connectivity and coherency. Within tightly integrated accelerator platforms, technologies such as NVLink and Infinity Fabric provide specialized high-performance communication. UALink represents an effort to bring open standards to large accelerator fabrics.

The resulting architecture is less like a traditional computer and more like a hierarchy of interconnected compute and memory resources.

🎯 Conclusion

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Interconnect technology has become one of the defining architectural factors in modern AI computing.

PCIe remains the universal foundation for connecting high-performance devices. NVLink and NVSwitch provide tightly integrated high-bandwidth communication for NVIDIA accelerator systems. CXL introduces cache-coherent connectivity between processors, accelerators, and memory. Infinity Fabric provides AMD with a scalable architecture for multi-die and accelerator systems. UALink seeks to establish a more open accelerator ecosystem, while UCIe standardizes communication between chiplets inside advanced packages.

As AI models continue to expand and accelerator systems move toward rack-scale and chiplet-based designs, simply adding more compute is no longer enough. Data must move between those compute resources efficiently.

The future of AI performance will therefore depend not only on faster GPUs and larger memory systems, but also on the high-bandwidth, low-latency interconnect fabrics that tie the entire architecture together.