NVIDIA Feynman GPU Targets TSMC A16 for 2028 Launch
NVIDIA’s next-generation Feynman GPU architecture is reportedly moving directly to TSMC’s A16 1.6nm-class process, bypassing the N2 family of nodes.
Expected to enter mass production in the second half of 2028, Feynman represents a significant evolution beyond Rubin and Rubin Ultra. Rather than relying solely on a smaller process node, NVIDIA is reportedly combining A16’s backside power delivery with increasingly aggressive 2.5D and 3D packaging technologies.
The architecture is also expected to pair with a customized HBM memory subsystem, potentially based on HBM4E, further emphasizing NVIDIA’s shift toward fully integrated AI computing platforms rather than conventional monolithic GPUs.
⚙️ Feynman Moves Directly to TSMC A16 #
NVIDIA is reportedly progressing prototype development of Feynman as the successor to the Rubin generation.
Instead of adopting TSMC’s N2-series nodes, the architecture is expected to move directly to A16, TSMC’s 1.6nm-class process technology.
Mass production is currently projected for H2 2028.
The decision is notable because process-node transitions are normally incremental. Skipping an entire node family suggests that NVIDIA sees greater system-level value in combining A16 with advanced power delivery and packaging technologies rather than pursuing every intermediate manufacturing generation.
Backside Power Delivery #
One of the key advantages of A16 is its backside power delivery architecture.
Conventional semiconductor designs route power and signals through the same general front-side interconnect infrastructure. Backside power delivery moves portions of the power network to the rear of the silicon, potentially reducing routing congestion and improving power delivery to densely packed logic.
For a high-power AI accelerator, these improvements can be particularly important as transistor density and compute throughput continue to increase.
🧩 Feynman Combines 3D and 2.5D Packaging #
Feynman is expected to use several advanced packaging technologies simultaneously rather than relying on a single integration method.
The reported design includes:
- SoIC 3D chiplet stacking
- CoWoS-L 2.5D integration
- CoPoS or related panel-level packaging
- A16 backside power delivery
This combination allows NVIDIA to separate a large compute system into multiple specialized dies while maintaining extremely high-bandwidth communication between them.
SoIC 3D Chiplet Integration #
TSMC’s SoIC technology enables dies to be stacked vertically using high-density interconnects.
For Feynman, 3D chiplet integration could shorten communication paths between compute components while increasing the amount of silicon that can be integrated into a single package.
The approach also provides greater flexibility than a single enormous monolithic die. Individual chiplets can potentially be optimized for different functions and manufacturing requirements before being assembled into the final accelerator package.
CoWoS-L and Next-Generation Packaging #
The vertically stacked chiplets are reportedly expected to be integrated horizontally through CoWoS-L or related packaging technologies.
This creates a hybrid architecture combining vertical 3D stacking with horizontal 2.5D integration.
At the system level, such an approach could enable extremely dense accelerator packages with power consumption potentially reaching the kilowatt class and compute throughput measured in the tens of petaflops, depending on the final configuration.
These figures should be treated as architectural targets rather than confirmed specifications until NVIDIA discloses the production implementation.
🧠 Customized HBM Could Become Part of the Compute Architecture #
Feynman is also expected to introduce a more tightly integrated memory architecture.
During mass production, NVIDIA will reportedly pair the GPU with a customized HBM solution, with HBM4E considered a likely candidate.
Rather than treating HBM purely as an external high-bandwidth memory component, the customized implementation could incorporate additional logic into the memory stack’s base die.
Logic-Enhanced HBM #
The base die could potentially contain functions such as:
- Memory controllers
- Data-movement logic
- Packet-processing functions
- Data preprocessing engines
- Other accelerator-specific logic
This approach effectively turns the memory subsystem into an active component of the computing platform.
Instead of transferring every operation directly between the GPU and conventional memory interfaces, some preprocessing or data-management tasks could occur closer to the memory itself.
The exact implementation will depend on NVIDIA’s final product architecture and the capabilities offered by its HBM partners.
🔬 Why the A16 Decision Matters #
Moving directly to A16 gives NVIDIA an opportunity to combine several technology transitions within the same generation.
The resulting platform is not simply a smaller GPU. It potentially represents simultaneous changes across:
- Transistor technology through A16
- Power delivery through backside power routing
- Compute architecture through chiplet decomposition
- Package integration through SoIC and CoWoS-L
- Memory architecture through customized HBM
- System-level bandwidth through tighter compute-memory integration
This is increasingly important for AI accelerators because raw transistor density is no longer the only constraint.
As accelerator performance scales, power delivery, memory bandwidth, thermal density, inter-die communication, and package size increasingly determine how much useful compute can actually be delivered.
🔭 Feynman Signals a Shift Toward System-Level GPU Design #
The reported Feynman architecture illustrates how NVIDIA’s future GPUs are evolving beyond the traditional concept of a single graphics processor.
A Feynman-class accelerator could instead be viewed as a tightly integrated system composed of multiple compute chiplets, high-bandwidth memory stacks, power-delivery infrastructure, and advanced optical or electrical interconnects.
That direction is consistent with the broader evolution of AI hardware.
As models become larger and inference and training workloads demand greater data movement, the performance ceiling increasingly depends on how efficiently compute, memory, and interconnects operate together.
NVIDIA’s decision to target TSMC A16 rather than N2, combined with aggressive 3D and 2.5D packaging, suggests that Feynman is being designed around this system-level constraint from the outset.
🏁 Feynman Could Redefine NVIDIA’s Next AI Accelerator Generation #
If the reported roadmap holds, NVIDIA’s Feynman generation will represent a substantial architectural transition beyond Rubin.
The combination of TSMC A16, backside power delivery, SoIC 3D chiplets, CoWoS-L packaging, and customized HBM4E-class memory could allow NVIDIA to scale compute density and memory bandwidth far beyond conventional GPU packaging approaches.
The most important question will ultimately be whether NVIDIA can translate this extremely complex technology stack into a manufacturable, thermally manageable, and economically viable production platform.
With mass production currently expected in H2 2028, there is still considerable time for specifications and implementation details to change. Nevertheless, the reported decision to skip N2 and move directly to A16 provides an important indication of how NVIDIA is approaching the next phase of AI accelerator scaling: not simply through smaller transistors, but through deeper integration of compute, power, memory, and packaging.