The AMD EPYC™ 9005 series marks the fifth generation of AMD’s data center processors, bringing together cutting-edge Zen 5 cores, next-generation I/O dies, expanded memory bandwidth, and advanced security — all within the proven SP5 socket.
This guide offers a high-level overview of the architecture, internal structure, and performance-enhancing features that define AMD’s latest server-class CPUs.
🧩 Chapter 1: Introduction #
The AMD EPYC™ 9005 series represents AMD’s most refined EPYC architecture to date. Built on the Zen 5 microarchitecture, these CPUs integrate higher memory bandwidth, improved interconnects, and a next-gen I/O Die (IOD) to enhance scalability and performance efficiency.
General Specifications #
The EPYC 9005 lineup offers a wide range of configurations tailored for diverse workloads — varying in core count, TDP, frequency, and cache size — providing flexible deployment options across hyperscale, cloud, and enterprise data centers.
AMD recommends using the latest supported operating systems for optimal stability and performance. Refer to the EPYC Processor Minimum OS Versions document for compatibility details.
⚙️ Chapter 2: Architectural Overview #
The EPYC 9005 processors maintain AMD’s multi-chip module (MCM) design, integrating compute, memory, I/O, reliability, and security into a single System-on-Chip (SoC). The architecture combines multiple Core Complex Dies (CCDs) surrounding a central I/O Die, all interconnected by Infinity Fabric™.
Zen 5 Compute Cores #
At the heart of each EPYC 9005 is the Zen 5 core, designed for improved Instructions Per Cycle (IPC), better branch prediction, and enhanced cache utilization. Each core includes:
- 32 KB 8-way L1 instruction cache and 48 KB 12-way L1 data cache
- 1 MB private 16-way L2 cache
- Shared 32 MB L3 cache per Core Complex (CCX)
Each core supports Simultaneous Multi-Threading (SMT), running two threads per core. All cores share identical ISA compatibility across SKUs.
Core Complex (CCX) #
Each CCX groups up to eight Zen 5 (Classic) or sixteen Zen 5c (Dense) cores sharing a unified 32 MB L3 cache. SMT effectively doubles the concurrent thread capacity to 16 or 32 threads per CCX.
Core Complex Die (CCD) #
Each CCD integrates one CCX. System BIOS allows selective core disablement to fine-tune performance and cache ratios:
- Per-CCD core reduction: Improves cache-per-core ratio.
- CCD deactivation: Maintains cache sharing efficiency with fewer dies.
Infinity Fabric™ and I/O Die (IOD) #
The I/O Die (IOD) acts as the communication hub, linking all CCDs, memory controllers, and I/O subsystems through Infinity Fabric™. Each CCD connects via a Global Memory Interconnect (GMI) link, maintaining cache coherency and scalability across sockets.
Key connectivity features include:
- Up to 4 xGMI (G-links) at 32 Gbps for processor interconnects
- PCIe® Gen5 and CXL 2.0 support
- 12 Unified Memory Controllers (UMCs) for DDR5
- 4 P-links configurable for I/O or memory expansion
In “wide” OPNs, each CCD connects to dual GMI interfaces, doubling core-to-I/O bandwidth.
Memory, I/O, and Connectivity #
Each EPYC 9005 supports up to 9 TB of DDR5 memory, distributed across 12 channels and 2 DIMMs per channel (DPC). This enables:
- 1DPC (lower latency) or 2DPC (maximum capacity) operation
- Cross-channel memory interleaving for workload optimization
- Up to 128 PCIe Gen5 lanes in single-socket and 160 lanes in dual-socket configurations
CXL 2.0 support enables expanded memory and high-speed interconnect options.
🧠 Chapter 3: NUMA Topology and Configuration #
The EPYC 9005 series employs a Non-Uniform Memory Access (NUMA) topology. Each processor can be segmented into multiple NUMA nodes using BIOS NPS (NUMA per Socket) settings to balance memory access latency and core locality.
NUMA Modes #
- NPS=4 → 4 NUMA nodes per socket (best for quadrant locality)
- NPS=2 → 2 nodes per socket, each with 6 memory channels
- NPS=1 → Unified memory space per socket
- NPS=0 → Single NUMA domain across dual sockets
Advanced tuning via LLC-as-NUMA allows treating each L3 cache (CCX) as a separate NUMA node for even finer workload locality control.
Note: Software should always query NUMA topology through OS APIs rather than relying on static APICID or CCX order assumptions.
Dual-Socket Configuration #
Dual-socket (2P) systems connect via xGMI/Infinity Fabric links, providing high-bandwidth, low-latency interconnects. Depending on configuration:
- 4 links → maximum inter-socket bandwidth (128 PCIe lanes total)
- 3 links → more PCIe lanes (up to 160 total) at slightly reduced fabric bandwidth
Each socket retains 12 DDR5 channels, ensuring balanced memory throughput across configurations.
🧾 Chapter 4: Processor Identification #
AMD’s naming convention for the EPYC 9005 helps decode the SKU’s architecture, core type, and thermal design.
CPUID Instruction #
Software can identify the processor using the CPUID (Fn0000_0001_EAX) instruction:
- Family: 1Ah → Zen 5 architecture
- Model: Varies by stepping (e.g., 10h for Zen 5 “A” stepping)
- Stepping: Indicates minor revisions (e.g., 25,17,1 = B1 stepping)
🔒 Chapter 5: Additional Features and ISA Updates #
Fifth-generation EPYC CPUs introduce several improvements over previous models, including:
- AVX-512: Full 512-bit SIMD execution
- VP2INTERSECT: New instruction for optimized vector processing
- Expanded security features and RAS (Reliability, Availability, Serviceability)
- Updated AMD64 ISA extensions
For full architectural and programming reference, consult the latest AMD64 Architecture Programmer’s Manual.
🧭 Summary #
The AMD EPYC 9005 (Turin) architecture delivers a balance of compute density, I/O scalability, and energy efficiency. Its combination of Zen 5 cores, Infinity Fabric interconnects, and advanced NUMA configurability makes it a powerhouse platform for next-generation data centers.