Intel Nova Lake May Retain Full L3 Cache on Trimmed SKUs
Recent leaks surrounding Intel’s upcoming Nova Lake processors suggest that reducing the number of Efficient-core (E-core) clusters may not always result in a corresponding reduction in native L3 cache.
Two previously reported mainstream configurations have reportedly received higher L3 cache estimates, with the revised capacities matching those of their fully enabled counterparts. However, the adjustment does not appear to follow a consistent rule across the lineup.
The leaked cache configurations reportedly apply to both desktop Nova Lake processors and mobile Nova Lake-HX parts. Intel has not officially confirmed these specifications, and the final product stack may change before launch.
🧩 Select Nova Lake SKUs May Keep Full L3 Cache #
Earlier leaks suggested that Nova Lake configurations with reduced E-core counts would also receive proportionally smaller L3 cache allocations.
The latest information changes that assumption for at least two configurations.
The reported revisions are:
| CPU configuration | Previous L3 estimate | Revised L3 estimate |
|---|---|---|
| 8P + 12E | 33 MB | 36 MB |
| 4P + 4E | 15 MB | 18 MB |
In both cases, the revised L3 capacity reportedly matches the amount available on the corresponding fully enabled configuration.
This suggests that Intel may be disabling E-core resources without necessarily disabling an equivalent portion of the cache associated with the underlying silicon configuration.
Cache Capacity Does Not Always Scale With E-Core Count #
The distinction is important because core-count reductions and cache reductions are not necessarily linked at the architectural level.
If a CPU die contains physically available cache resources that can remain enabled after certain E-core clusters are disabled, Intel may choose to retain those cache blocks depending on the intended SKU configuration, yields, segmentation strategy, or other product-level considerations.
As a result, a processor with fewer active E-cores does not automatically have to expose less L3 cache.
🔍 Other Trimmed Configurations Still Lose L3 Cache #
The revised estimates do not indicate that Intel is universally retaining full L3 cache across all E-core-trimmed Nova Lake SKUs.
The 6P + 12E configuration provides a notable counterexample. It is reportedly assigned 27 MB of L3 cache, compared with 30 MB on the corresponding fully configured tier.
That means this configuration still carries a cache reduction despite having its E-core configuration trimmed.
There is currently no publicly established formula explaining why some configurations retain their complete L3 capacity while others do not.
SKU-Specific Cache Allocation May Be the Explanation #
The inconsistent cache behavior suggests that Intel could be making cache allocations on a SKU-by-SKU basis rather than applying a simple rule tied directly to active P-core or E-core counts.
Several factors could potentially influence the decision, including die segmentation, product positioning, manufacturing yields, disabled core clusters, and the physical organization of cache resources.
Until Intel publishes official architectural and product documentation, however, any explanation remains speculative.
The same general cache-allocation behavior is reportedly visible across both desktop Nova Lake and Nova Lake-HX mobile processors.
🧠 bLLC Remains Separate From Native L3 Cache #
Nova Lake is also expected to introduce bLLC (base-die Last Level Cache) to Intel’s consumer desktop platform.
The technology is positioned as a major cache-based performance feature and is expected to compete with AMD’s approach to large additional cache capacity, including 3D V-Cache.
Importantly, bLLC is separate from the native L3 cache discussed in the latest leaks.
Changes to native L3 capacity therefore do not imply corresponding changes to bLLC.
Reported bLLC Configurations Remain Unchanged #
Current leaks indicate that bLLC will be reserved for mid- to high-end Nova Lake configurations.
The reported capacities are:
- 8 + 12 + 4 configuration: 132 MB of bLLC
- 6 + 12 + 4 configuration: 108 MB of bLLC
Neither configuration has reportedly changed in the latest revisions.
This distinction means Nova Lake’s total effective cache hierarchy could vary considerably between SKUs even when their native L3 configurations appear similar.
⚠️ Nova Lake Specifications Remain Unconfirmed #
The latest cache revisions provide an interesting look at how Intel may segment Nova Lake processors, particularly when disabling E-core clusters.
The most notable change is that the 8P + 12E and 4P + 4E configurations are now reportedly expected to retain 36 MB and 18 MB of L3 cache, respectively, despite their reduced E-core configurations.
However, the 6P + 12E configuration reportedly remains at 27 MB rather than receiving the full 30 MB allocation, demonstrating that there is no obvious universal relationship between E-core reductions and L3 cache capacity.
Meanwhile, the reported bLLC configurations remain unchanged, reinforcing that Intel’s base-die cache is a separate component of the Nova Lake cache hierarchy.
All of these specifications remain based on unofficial leaks. Intel has yet to formally confirm Nova Lake’s final core configurations, cache capacities, SKU segmentation, or launch specifications, so these figures should be treated as preliminary until official documentation becomes available.