Designing an embedded network interface requires understanding how Ethernet functionality is partitioned across hardware blocks and how those blocks are connected on a PCB. This article introduces the core architectural concepts behind embedded Ethernet, focusing on MAC/PHY separation, interface standards, and practical hardware design decisions.
🌐 Introduction to Embedded Networking #
In traditional PCs, networking is handled by a discrete Network Interface Card (NIC). In embedded systems, however, Ethernet functionality is usually integrated directly into the SoC and divided into two logical components:
- MAC (Media Access Control): Handles Ethernet framing, addressing, and DMA.
- PHY (Physical Layer): Handles electrical signaling, encoding, and link negotiation.
When an SoC datasheet claims to “support Ethernet,” it almost always means the SoC integrates a MAC, not a PHY. Just like I2C or SPI controllers, the MAC is an internal peripheral and cannot operate alone—it must be paired with an external PHY chip.
🧩 SoC Ethernet Architecture Options #
SoC Without an Internal MAC #
If an SoC does not include a MAC, Ethernet support must be added using an external MAC+PHY solution.
Common approaches include:
- Parallel-interface chips
Devices such as the DM9000 expose an SRAM-like bus to the SoC and integrate both MAC and PHY. - TCP/IP offload chips
Chips like the W5500 implement the full TCP/IP stack internally and communicate with the SoC over SPI. These are popular in MCU-based designs.
Advantages
- Enables Ethernet on processors with no native support
Limitations
- No dedicated DMA
- Lower throughput (typically 10/100M)
- Higher latency and BOM cost
SoC With Integrated MAC #
Most modern SoCs (for example, STM32F4/F7/H7, NXP i.MX series) include an on-chip MAC.
Key benefits
- High performance: Dedicated Ethernet DMA engines
- Higher speeds: Supports 10/100M and often Gigabit Ethernet
- Flexibility: Broad PHY selection and lower overall system cost
In this architecture, the MAC connects to an external PHY using MII or RMII for data transfer and MDIO for management.
🔌 Data Interfaces: MII vs RMII #
The data interface defines how Ethernet frames move between the MAC and PHY.
MII (Media Independent Interface) #
MII is the original IEEE-802.3 standard interface.
- Requires 16 signal lines
- Uses separate transmit and receive clocks generated by the PHY
Drawback:
High pin count increases PCB routing complexity and SoC pin usage.
RMII (Reduced Media Independent Interface) #
RMII is a simplified alternative designed for embedded systems.
- Uses only 7 signal lines
- Relies on a shared 50 MHz reference clock (REF_CLK)
Why it matters:
RMII dramatically reduces pin count and routing difficulty, making it the dominant choice for 10/100M embedded designs.
⚙️ Control Interface: MDIO #
The MDIO (Management Data Input/Output) interface is a two-wire serial bus consisting of:
- MDIO: Data
- MDC: Clock
MDIO is conceptually similar to I²C and allows software to read and write PHY registers. Key characteristics:
- Supports up to 32 PHY devices on a single bus
- PHYs are selected via hardware-configured addresses
- Used by the OS to configure speed, duplex, and link state
🔗 Physical Connection: RJ45 and Magnetics #
Ethernet PHYs cannot connect directly to an RJ45 connector. A network transformer (magnetics) is required between them.
Functions of magnetics
- Electrical isolation
- Noise filtering
- Impedance matching
Many modern designs use RJ45 connectors with integrated magnetics (for example, HR911105A). If a plain RJ45 jack is used, a discrete transformer circuit must be added to the PCB.
🧠 PHY Chip Fundamentals #
Ethernet PHYs expose 32 registers, addressed via MDIO:
- Registers 0–15:
IEEE-standardized and identical across vendors
→ Enables the Linux Generic PHY Driver to work out of the box - Registers 16–31:
Vendor-specific features such as power saving, cable diagnostics, or tuning
This standardization is what makes Ethernet PHY integration relatively painless in Linux-based systems.
✅ Design Recommendations #
For new embedded designs:
- Prefer an SoC with an integrated MAC
- Use RMII for most 10/100M applications
- Select PHYs with good Linux support and reference designs
- Use integrated-magnetics RJ45 connectors to simplify layout
This approach provides the best balance of performance, cost, and design simplicity for modern embedded Ethernet systems.