Why Ethernet Is Taking Over AI Data Center Networking
For years, AI data center networking has been divided between two fundamentally different architectures: Scale-Up and Scale-Out.
Scale-Out connects large numbers of servers and accelerator nodes into distributed computing clusters. Scale-Up connects accelerators more tightly, allowing multiple GPUs to operate as a much larger logical computing system.
These two domains have traditionally relied on different technologies. Ethernet and InfiniBand have competed in Scale-Out networking, while proprietary interconnects such as NVIDIA NVLink have dominated high-performance Scale-Up architectures.
That separation is beginning to change.
Ethernet, once considered insufficient for the most demanding accelerator-to-accelerator workloads, is expanding into both networking domains. Advances in switching silicon, optical connectivity, congestion management, and open industry standards are making Ethernet a more credible option for tightly coupled AI systems.
Industry forecasts cited in the market outlook place the global AI data center networking opportunity near $200 billion by 2030. Ethernet is positioned to capture a substantial share of that growth.
The underlying shift is bigger than a change in networking protocols. It represents an attempt to move AI infrastructure away from fragmented, vendor-specific interconnect ecosystems toward a more interoperable networking architecture.
Three developments explain this transition: the convergence of Scale-Up and Scale-Out requirements, the adoption of Co-Packaged Optics (CPO), and the emergence of Ethernet-based Scale-Up standards such as ESUN.
🧱 Scale-Up and Scale-Out Are Converging #
Understanding Ethernet’s expanding role requires separating the two main networking domains.
Although both move data between computing devices, they operate under different performance constraints and serve different architectural purposes.
Scale-Out: Connecting Distributed AI Clusters #
Scale-Out networking connects servers, racks, and larger computing domains.
In distributed AI training, thousands of accelerators may need to exchange gradients, parameters, activations, and other intermediate data. The network must support high aggregate bandwidth while controlling latency, congestion, and packet loss.
Traditional Scale-Out architectures commonly use InfiniBand or Ethernet.
Ethernet deployments frequently rely on RoCEv2 (RDMA over Converged Ethernet), which allows applications to use Remote Direct Memory Access over an Ethernet infrastructure.
However, achieving predictable performance at large scale requires more than installing high-speed switches.
Congestion control, adaptive routing, load balancing, packet recovery, and collective communication all influence how efficiently an AI cluster operates.
This is one reason Ethernet’s evolution for AI networking involves changes across the entire protocol stack rather than simply increasing link speeds.
Scale-Up: Connecting Accelerators Into a Larger Computing System #
Scale-Up networking addresses communication between tightly coupled accelerators.
The objective is to allow multiple GPUs or other accelerators to exchange data at extremely high bandwidth and low latency, effectively behaving as a larger computing domain.
These systems often support operations involving frequent synchronization, memory access, and collective communication.
Unlike conventional Scale-Out networking, Scale-Up architectures may require more specialized mechanisms for flow control, switching, and communication between accelerators.
NVIDIA’s NVLink and NVSwitch ecosystem has historically been a leading example.
By integrating accelerator architecture, switching silicon, interconnect technology, and software, NVIDIA can optimize communication across its GPU systems.
This vertical integration is difficult for conventional Ethernet vendors to replicate.
However, it also creates an opportunity for alternative accelerator manufacturers and hyperscalers that want greater control over their infrastructure.
Why the Architectural Boundary Is Changing #
Scale-Up and Scale-Out were once treated as largely separate networking markets.
That distinction is becoming less rigid as AI systems expand across larger physical and logical domains.
Scale-Up fabrics can extend beyond a single server or rack, while Scale-Out architectures increasingly need to support communication patterns that place demanding requirements on latency and collective operations.
The distinction is therefore primarily about communication requirements and system architecture, not simply physical distance.
Ethernet vendors want to use the technology’s established switching ecosystem and manufacturing scale to address both domains.
If successful, this would allow customers to build more of their AI infrastructure around a common networking technology without necessarily depending on one accelerator vendor’s proprietary interconnect.
🔌 CPO Is Expanding Ethernet’s Physical Capabilities #
As Ethernet switch bandwidth advances toward 800G, 1.6T, and beyond, conventional pluggable optical modules face increasing power and signal-integrity constraints.
The challenge is not simply transmitting more bits.
Higher-speed electrical interfaces require increasingly sophisticated signal processing, while the power consumed by SerDes, DSPs, and optical transceivers becomes a significant part of overall system power.
Co-Packaged Optics offers another approach.
Instead of placing optical transceivers at the front panel and connecting them to the switch ASIC through relatively long electrical traces, CPO places optical engines much closer to the switching silicon.
This reduces the electrical distance between the switch ASIC and optical conversion interface.
How CPO Changes Switch Architecture #
CPO integrates optical engines into the same package or closely integrated assembly as the switch ASIC.
The architecture offers several potential advantages:
- Reduced electrical signal travel distance.
- Lower electrical I/O power consumption.
- Higher optical bandwidth density.
- Reduced dependence on long, high-speed electrical connections.
- Greater flexibility in scaling aggregate switch bandwidth.
These characteristics become increasingly relevant as switch capacity increases.
However, CPO also introduces engineering challenges involving thermal management, optical coupling, packaging yield, testing, and field repairability.
Unlike conventional pluggable modules, integrated optical engines are more difficult to replace independently.
The economic case therefore depends on whether improvements in power efficiency and bandwidth density outweigh the additional packaging and maintenance costs.
Why CPO Matters to Ethernet Scale-Up #
CPO does not define an Ethernet protocol or automatically make Ethernet suitable for Scale-Up workloads.
Its contribution is physical.
By improving the way high-speed electrical and optical interfaces are integrated, CPO can help Ethernet switching platforms support higher aggregate bandwidth within increasingly restrictive power and density budgets.
This becomes particularly relevant when Ethernet moves closer to accelerator systems.
A Scale-Up fabric needs substantial bandwidth, low communication overhead, and predictable performance. As these systems grow, the physical limitations of conventional electrical connectivity become harder to manage.
CPO and other advanced optical integration technologies provide additional options for addressing those constraints.
Pluggable optics will remain relevant across many applications, but CPO is becoming an increasingly important part of the industry’s long-term bandwidth roadmap.
🌍 Scale-Out: Ethernet Is Strengthening Its Position #
Ethernet already has a substantial presence in data center networking.
Its advantages include a mature supply chain, broad vendor support, established operational expertise, and compatibility with a large ecosystem of networking software and hardware.
For hyperscalers operating thousands of servers, these factors matter.
A networking architecture must be economical to deploy, straightforward to operate, and capable of scaling across multiple generations of infrastructure.
The Ultra Ethernet Consortium Changes the Equation #
The Ultra Ethernet Consortium (UEC) was established to adapt Ethernet for AI and high-performance computing workloads.
Its work targets several limitations of conventional Ethernet deployments, particularly those involving congestion, transport efficiency, reliability, and collective communication.
The goal is not simply to increase link bandwidth. It is to improve how Ethernet behaves under the demanding traffic patterns generated by distributed AI workloads.
Key areas include:
- Improved congestion management.
- More efficient transport protocols.
- Better handling of packet loss and recovery.
- Adaptive routing and load balancing.
- Support for RDMA-based communication.
- Optimizations for collective operations.
These improvements matter because AI training traffic can produce substantial bursts of synchronized communication.
A network that performs well under ordinary data center traffic may behave differently when thousands of accelerators simultaneously exchange large volumes of data.
UEC aims to address these requirements through a more specialized Ethernet architecture.
The Scale-Out Market Opportunity #
The economic case for Ethernet is particularly strong in large distributed AI clusters.
The global Ethernet ecosystem already includes established switch manufacturers, semiconductor suppliers, optical component vendors, and network software providers.
This reduces the need for customers to build their infrastructure around a completely separate proprietary networking ecosystem.
Market forecasts cited in the original industry outlook suggest that AI Scale-Out Ethernet revenue could exceed $100 billion by 2030.
Optical connectivity is another major beneficiary.
800G and 1.6T pluggable modules, together with emerging CPO architectures, are expected to capture a growing portion of high-speed switch system value.
One cited market estimate places their combined contribution above 50% of switch revenue in relevant high-bandwidth configurations by 2030.
These figures should be treated as forward-looking estimates rather than guaranteed market outcomes. Actual adoption will depend on deployment economics, product availability, and the pace at which AI infrastructure expands.
For Ethernet vendors, the opportunity is clear: AI networking is creating demand for higher-capacity switches, faster optical interfaces, and increasingly sophisticated network silicon.
🔄 Scale-Up: Ethernet Challenges NVIDIA’s NVLink Ecosystem #
Scale-Up networking has historically been one of the strongest areas of differentiation for NVIDIA.
NVLink and NVSwitch provide a tightly integrated communication architecture for connecting GPUs within large accelerator systems.
The advantage comes from system-level optimization.
NVIDIA controls the accelerator, interconnect, switching architecture, and much of the supporting software ecosystem. This allows it to optimize communication performance across the entire platform.
Ethernet vendors face a different challenge.
They need to deliver comparable system-level capabilities while preserving the interoperability and flexibility that make open networking attractive.
From UALink and SUE to ESUN #
Several alternative Scale-Up approaches have emerged.
Two notable examples are UALink and Broadcom’s Scalable Unified Ethernet (SUE) initiative.
UALink was designed to provide an open accelerator interconnect specification, with an architecture targeting high-bandwidth, low-latency communication between accelerators.
Broadcom’s SUE takes a different approach by using Ethernet-oriented packet transport for Scale-Up communication.
These approaches reflect different engineering priorities.
UALink focuses on a dedicated accelerator interconnect architecture, while SUE attempts to extend Ethernet’s existing technology foundation into tightly coupled accelerator systems.
The existence of competing approaches initially created uncertainty around the future standards landscape.
This fragmentation helped motivate the formation of ESUN.
What Is ESUN? #
ESUN stands for Ethernet for Scale-Up Networking.
It emerged in late 2025 as an industry initiative to develop an Ethernet-based framework for accelerator Scale-Up networking.
Its central objective is to make Ethernet a viable transport foundation for communication between tightly coupled accelerators.
The main architectural goals include:
- Standardizing Ethernet as the underlying networking technology.
- Supporting Scale-Up traffic patterns and communication requirements.
- Allowing compatible implementations to use Ethernet switching silicon.
- Reducing dependence on proprietary accelerator interconnect ecosystems.
- Enabling interoperability across multiple hardware vendors.
The distinction between ESUN and conventional Ethernet networking is important.
Simply connecting accelerators through an ordinary Ethernet switch does not automatically provide the latency, flow control, and communication characteristics required by Scale-Up workloads.
Specialized transport behavior and hardware support are still necessary.
ESUN is intended to address these requirements while retaining the advantages of a common Ethernet technology base.
The 2030 Scale-Up Revenue Opportunity #
The original market outlook provides the following estimates for competing interconnect technologies:
| Technology | Estimated 2030 Revenue |
|---|---|
| NVIDIA NVLink | Approximately $25 billion |
| Ethernet Scale-Up (ESUN) | $8 billion or more |
| PCIe / UALink | Approximately $3 billion |
These figures represent market projections, not confirmed revenue or standardized industry forecasts.
The underlying competitive dynamic is more significant than the precise numbers.
NVLink is not likely to disappear simply because Ethernet-based alternatives emerge. Its close integration with NVIDIA’s accelerator and software platforms provides advantages that are difficult to reproduce.
However, Ethernet Scale-Up introduces another option for customers that want to avoid depending entirely on one vendor’s proprietary interconnect.
The competition is shifting from exclusivity toward architectural choice.
For a deeper look at the development of open Ethernet Scale-Up architectures, see Arista SU-144 Challenges NVLink With Open Ethernet Scale-Up.
🏭 Established Vendors and Startups Face Different Opportunities #
The expansion of Ethernet into Scale-Up networking creates opportunities across several parts of the semiconductor and networking supply chain.
However, the requirements for established vendors and startups are quite different.
Established Vendors: Broadcom, Cisco, and Other Networking Suppliers #
Established networking companies already possess substantial advantages.
They have experience developing high-performance switch ASICs, Ethernet PHYs, SerDes technology, optical connectivity, and networking software.
Their existing customer relationships also provide access to hyperscale infrastructure projects.
The emergence of CPO and Ethernet Scale-Up creates an opportunity to move into higher-value system architectures.
Rather than competing exclusively for conventional data center switch sockets, vendors can pursue accelerator networking platforms that previously relied on proprietary interconnect technologies.
However, the engineering requirements are demanding.
Competing with NVIDIA requires more than matching switch bandwidth.
Vendors must demonstrate:
- Low and predictable communication latency.
- Efficient congestion management.
- High-bandwidth accelerator connectivity.
- Reliable collective communication.
- Compatible software and hardware implementations.
- Competitive system-level power consumption.
CPO adds another layer of complexity because optical engines, switch ASICs, packaging, and thermal management need to work together.
Companies that can integrate these technologies effectively will have more opportunities to participate in next-generation AI infrastructure.
Startups: Finding a Reason to Replace Established Architectures #
Startups also have an opportunity.
Hyperscalers increasingly want alternatives to proprietary infrastructure, particularly as AI accelerator deployments become more heterogeneous.
This creates room for new switch architectures, optical interconnect technologies, specialized SerDes, and accelerator networking solutions.
However, entering this market is difficult.
A new architecture must offer a compelling advantage over established solutions.
That advantage could involve:
- Higher bandwidth density.
- Lower power consumption per bit.
- Reduced system cost.
- Better latency under real AI workloads.
- Improved scalability.
- Greater interoperability.
A tenfold improvement in a meaningful metric can help justify the engineering and operational risks associated with adopting a new technology.
But theoretical performance is not enough.
Startups must also demonstrate manufacturing readiness, software compatibility, production reliability, and a credible path to large-scale deployment.
For hyperscalers, switching infrastructure carries significant operational risk. A new solution must provide measurable benefits across the complete system, not merely outperform an incumbent in an isolated benchmark.
🌐 Ethernet Is Moving Toward a Unified AI Networking Fabric #
The competition between Scale-Up and Scale-Out is no longer simply a contest between separate networking technologies.
Both domains are evolving toward higher bandwidth, more sophisticated traffic management, and tighter integration with accelerator architectures.
Ethernet is positioned to benefit from this convergence because it already has an extensive ecosystem of switch silicon, optical components, networking software, and manufacturing partners.
Three developments are driving the transition:
- Scale-Out expansion: UEC and related technologies are adapting Ethernet to the traffic patterns and reliability requirements of large AI clusters.
- Scale-Up adoption: ESUN and other open interconnect initiatives are extending Ethernet-based architectures toward accelerator-to-accelerator communication.
- Optical integration: CPO and advanced optical technologies are addressing the power and signal-integrity constraints associated with increasing switch bandwidth.
However, a unified Ethernet fabric does not mean every AI system will use identical networking hardware or eliminate proprietary interconnects.
NVIDIA’s NVLink ecosystem will remain relevant wherever its integrated accelerator and networking architecture delivers advantages that customers value.
Similarly, hyperscalers may continue using specialized interconnects for their own accelerator platforms.
The more likely direction is coexistence: proprietary architectures serving tightly optimized computing systems, alongside open Ethernet-based solutions expanding across heterogeneous accelerator environments.
The decisive factor will be system-level performance and economics.
Ethernet does not need to replace every proprietary interconnect to become a central technology in AI infrastructure. It needs to provide a scalable, interoperable, and economically competitive alternative across an increasingly large portion of the networking stack.
As AI clusters grow, the companies controlling switch silicon, optical connectivity, SerDes, and network protocols will compete for a larger share of infrastructure spending.
The next phase of AI networking will therefore be determined not only by who builds the fastest accelerator, but also by who can move data between accelerators efficiently, reliably, and at scale.
