Cerebras CS-4, CS-5 and CS-6: Wafer-Scale AI Roadmap

Cerebras CS-4, CS-5 and CS-6: Wafer-Scale AI Roadmap

Cerebras has unveiled a three-generation roadmap for its wafer-scale AI computing platform, revealing detailed specifications for the Cerebras CS-4 and outlining the company’s future CS-5 and CS-6 AI accelerator architectures.

Presented at Hot Chips 2026, the roadmap shows how Cerebras plans to evolve its wafer-scale engine technology from a modular rack-scale deployment platform into increasingly efficient inference infrastructure and, ultimately, a three-dimensional wafer-scale computing architecture.

The CS-4 is currently in early access and is expected to reach general availability in Q3 2026. The 2027-generation CS-5 will focus heavily on LLM inference performance and tokens-per-watt efficiency, while the longer-term CS-6 is planned to introduce 3D-stacked wafer-scale SRAM, vertical power delivery, and integrated cooling.

Together, these products establish a multi-generation strategy around Cerebras’ Nexus modular rack platform, targeting the rapidly expanding market for high-performance and energy-efficient AI inference.

🚀 Cerebras CS-4 Brings Wafer-Scale Computing to a Modular Rack

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The Cerebras CS-4 is the first production AI system based on the company’s new Nexus rack architecture. Instead of deploying the wafer-scale processor as a standalone accelerator, Cerebras has designed CS-4 as a modular rack-scale system that combines multiple WSE-3 Turbo processors with dedicated power, cooling, and networking infrastructure.

A single CS-4 rack contains three WSE-3 Turbo (WSE-3T) processors and delivers:

• 750 PFLOPS of AI compute
• 7.2 Tb/s of system I/O bandwidth
• 129.6 PB/s of aggregate memory bandwidth
• Up to 2× higher token-generation speed than CS-3
• Up to 10× higher throughput per watt than CS-3
• Up to 30× faster inference than existing production GPU systems, according to Cerebras

These specifications position CS-4 primarily as an LLM inference platform, where memory bandwidth, communication latency, power efficiency, and token-generation speed can be more important than peak theoretical compute alone.

WSE-3 Turbo Delivers Higher Performance Without a Larger Wafer

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The WSE-3 Turbo maintains the core physical specifications of Cerebras’ WSE-3 architecture.

The processor still contains approximately 4 trillion transistors and 44 GB of on-chip SRAM, while maintaining the same wafer area and on-chip memory capacity.

Instead of increasing the physical size of the wafer, Cerebras raises operating frequencies to increase compute throughput. A single WSE-3T delivers up to 250 PFLOPS of FP16 compute, while its compute fabric, memory system, and I/O capabilities are substantially enhanced.

This strategy allows Cerebras to increase performance without depending on a larger wafer or fundamentally expanding the existing on-chip SRAM capacity.

Modular Compute Backpacks Improve AI System Serviceability

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One of the defining characteristics of CS-4 is its modular physical architecture.

Each WSE-3T is installed in an independent compute backpack containing dedicated power delivery, direct liquid cooling, and I/O components. This isolates the primary compute modules from the rest of the rack infrastructure.

Power supply units are positioned at the front of the rack, allowing the compute, power, and networking subsystems to be maintained independently.

This architecture can simplify deployment and servicing while allowing individual components to be upgraded without redesigning the entire rack.

Cerebras also reports a 50% reduction in component count compared with CS-3 and an increase in automated assembly to 60%. These manufacturing improvements are intended to reduce production complexity and help lower deployment and operating costs.

CS-4 Uses Ultra-Short Power Delivery Paths

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Power delivery is another major focus of the Cerebras CS-4 architecture.

Cerebras places its DC/DC converters approximately 0.5 mm from the WSE-3T, substantially shortening the electrical path between the power conversion stage and the processor.

Shorter power-delivery paths reduce losses associated with PCB traces and conventional board-level power distribution. Cerebras claims that this design can reduce board-level power loss by up to 100× compared with traditional GPU-oriented architectures.

For large AI accelerator systems, these improvements can have a direct impact on overall rack efficiency because power losses outside the processor itself increasingly contribute to total system consumption.

Cable-Free Interconnect Reaches 53.5 PB/s

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Cerebras continues to rely on extremely high-bandwidth communication within its wafer-scale architecture.

The CS-4 provides up to 53.5 PB/s of intra-wafer fabric bandwidth using a cable-free interconnect design. By reducing reliance on conventional external cabling for critical communication paths, Cerebras aims to minimize latency and communication overhead.

This is particularly relevant to large language model inference, where autoregressive token generation requires repeated movement and processing of model data. Lower communication latency can translate into faster response times and higher effective token-generation performance.

⚡ Cerebras CS-5 Targets 10,000 Tokens/s LLM Inference

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The next-generation Cerebras CS-5 is planned for 2027 and will continue using the reusable Nexus platform.

While CS-4 establishes the modular rack architecture, CS-5 is positioned primarily around AI inference efficiency and LLM performance. Cerebras intends the system to support models ranging from approximately 30 billion parameters to several trillion parameters.

The company’s current performance targets include:

• Up to 10,000 tokens/s for models such as Gemma 4 31B and gpt-oss 120B in single-user inference
• Up to 5,000 tokens/s for frontier models such as DeepSeek, Kimi, and GPT 5.6 SOL
• Up to 3 million tokens/s per megawatt of power consumption

If achieved in production, these targets would make CS-5 particularly relevant to latency-sensitive LLM serving and high-density AI inference deployments.

Tokens per Second and Tokens per Watt Become Key AI Metrics

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The CS-5 roadmap reflects a broader change in how AI accelerator performance is evaluated.

For AI training, peak FLOPS and aggregate cluster throughput remain important metrics. In production inference, however, system efficiency depends on a broader set of characteristics:

• Token-generation latency
• Tokens generated per second
• Tokens generated per watt
• Memory bandwidth
• Interconnect performance
• Model-serving density
• Power consumption
• System utilization

Autoregressive LLMs repeatedly execute model layers for every generated token. As parameter counts increase, moving model weights and intermediate data efficiently becomes a critical bottleneck.

Cerebras’ wafer-scale approach attempts to address this challenge by placing substantial compute and memory resources within a highly integrated architecture with extremely high internal bandwidth.

CS-5 is expected to build on this foundation with additional improvements focused specifically on inference throughput and energy efficiency.

🧊 Cerebras CS-6 Plans 3D Wafer-Scale Integration

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The Cerebras CS-6 represents the most ambitious architectural change in the company’s current roadmap.

While CS-6 remains in the planning and R&D phase, Cerebras intends to introduce 3D wafer-scale integration, stacking wafer-scale SRAM directly above the WSE processor using advanced 3D packaging technology.

The primary objective is to increase memory density and improve data access without expanding the processor’s horizontal footprint.

A vertically integrated SRAM architecture could potentially reduce memory-interconnect distances while increasing the amount of memory available close to the compute fabric. This could become increasingly important as AI models continue to grow and memory movement becomes a larger component of inference cost.

Cerebras plans to combine 3D memory integration with:

• Yield-resilient wafer-scale architecture
• Vertical power delivery
• Integrated cooling
• Higher-density system packaging

The combined approach is intended to reduce system footprint while creating additional performance headroom for future AI inference workloads.

3D Packaging Creates New Thermal and Manufacturing Challenges

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Moving to 3D wafer-scale integration introduces challenges that do not exist to the same extent in conventional planar designs.

Stacking SRAM directly above a large compute wafer increases packaging density but also makes thermal management, power delivery, and manufacturing yield significantly more complex.

High-density vertical integration requires efficient heat extraction from multiple layers while maintaining acceptable thermal gradients across a very large computational surface.

Cerebras’ planned yield-resilient architecture is therefore important because the company must preserve the fault-tolerance characteristics of wafer-scale computing while introducing substantially more complex packaging.

Cerebras has not yet disclosed final CS-6 specifications or a confirmed mass-production timeline.

📊 Cerebras CS-4 vs. CS-5 vs. CS-6 Roadmap

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The three generations represent a clear progression in Cerebras’ wafer-scale AI strategy.

Generation	Primary Objective	Key Technology
CS-4	Modular rack-scale AI deployment	Nexus platform and WSE-3T
CS-5	Faster and more efficient LLM inference	Higher tokens/s and tokens/W
CS-6	Higher compute and memory density	3D wafer-scale SRAM integration

The CS-4 focuses on establishing a scalable and serviceable rack architecture. CS-5 shifts the emphasis toward extreme inference performance and energy efficiency. CS-6 takes the architecture further by exploring three-dimensional integration at wafer scale.

This is more than a conventional generational accelerator upgrade. Cerebras is effectively optimizing the entire AI compute system across silicon, memory, interconnect, power delivery, cooling, and rack infrastructure.

🌐 How Cerebras’ Wafer-Scale Roadmap Could Change AI Computing

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Cerebras’ roadmap highlights the increasing diversification of the AI accelerator market.

Traditional GPU clusters provide broad programmability and benefit from mature software ecosystems. Cerebras instead takes a more vertically integrated approach, combining massive compute capacity with high-bandwidth on-chip memory and communication infrastructure.

This distinction becomes especially important as the AI industry moves from model training toward increasingly demanding inference workloads.

For production LLM infrastructure, the most meaningful performance indicators increasingly include:

• Tokens per second
• Tokens per watt
• Memory bandwidth
• Interconnect latency
• Inference throughput
• Model-serving density
• Rack-level power efficiency
• Cooling requirements
• Total deployment cost

Cerebras’ CS-4, CS-5, and CS-6 roadmap directly targets these system-level metrics.

Wafer-Scale AI Moves Beyond Raw FLOPS

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The significance of Cerebras’ roadmap is not simply the increase in raw compute performance.

The company’s architecture demonstrates an attempt to optimize the complete AI inference stack. Compute engines, SRAM, interconnects, power conversion, cooling, and rack infrastructure are designed as components of a unified system rather than isolated technologies.

CS-4 establishes this approach through the Nexus modular rack. CS-5 is expected to increase the amount of useful inference work delivered per unit of power. CS-6 then explores 3D packaging as a way to increase memory density and reduce the physical footprint of wafer-scale systems.

If Cerebras can achieve its projected performance and efficiency targets while maintaining reliable manufacturing and scalable deployment, wafer-scale computing could become a more significant alternative to conventional GPU clusters for high-volume LLM inference and AI serving.

As model sizes continue to increase and inference demand expands, the competitive advantage may increasingly come not from peak accelerator FLOPS alone, but from how efficiently an entire rack converts electrical power into useful tokens.