AHB vs APB Explained: Understanding ARM On-Chip Bus Architecture

AHB vs APB Explained: Understanding ARM On-Chip Bus Architecture

Embedded developers are typically familiar with external communication buses such as I2C, SPI, UART, CAN, and Ethernet. These protocols enable communication between chips, sensors, peripherals, and external devices.

However, modern MCUs and SoCs also rely heavily on another category of communication infrastructure: on-chip buses.

Unlike off-chip protocols, on-chip buses operate entirely inside the processor or microcontroller. They connect the CPU core, memory subsystems, DMA engines, and peripheral controllers through dedicated hardware interconnects. Since these buses are implemented directly in silicon and managed automatically by hardware, firmware developers often overlook them.

Still, understanding internal bus architecture is essential for:

• Analyzing MCU performance bottlenecks
• Understanding peripheral latency
• Optimizing DMA throughput
• Debugging bus contention issues
• Learning how ARM-based SoCs are organized internally

Two of the most widely used on-chip buses in ARM systems are:

• AHB (Advanced High-performance Bus)
• APB (Advanced Peripheral Bus)

Both are part of the ARM AMBA (Advanced Microcontroller Bus Architecture) specification and serve distinct purposes within the system.

🚀 Understanding the AHB Bus

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AHB stands for Advanced High-performance Bus.

As the name suggests, AHB is designed for high-speed, high-bandwidth communication between performance-critical system components.

Typical AHB-connected devices include:

• CPU cores
• SRAM
• Flash memory
• DMA controllers
• High-speed peripherals

Its primary goal is maximizing throughput and minimizing latency.

AHB Bus Architecture

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AHB uses a multi-master, multi-slave architecture.

This differs significantly from simpler buses like SPI, which generally operate with a single master and multiple slaves.

In an AHB system:

• Multiple masters may initiate transfers simultaneously
• Multiple slaves may exist on the same interconnect
• Arbitration logic determines bus ownership

Typical AHB masters include:

• CPU cores
• DMA controllers
• Debug interfaces

Typical AHB slaves include:

• SRAM
• Flash
• Peripheral controllers
• External memory interfaces

Arbitration and Routing

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Because multiple masters can request access simultaneously, AHB requires an arbiter.

The arbiter:

• Resolves bus contention
• Grants bus ownership
• Ensures only one master drives the shared bus at a time

A central multiplexer interconnect routes:

• Address signals
• Control signals
• Read/write data

between the active master and the selected slave.

This routing infrastructure enables efficient resource sharing without signal collisions.

Parallel Bus Design

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Unlike serial protocols such as SPI or I2C, AHB is a parallel bus.

Parallel communication provides:

• Extremely high throughput
• Low latency
• Simultaneous multi-bit transfers

The tradeoff is increased signal count and shorter practical routing distance, which is acceptable for on-chip communication.

A typical 32-bit AHB implementation may require well over 100 signal lines depending on:

• Data width
• Address width
• Number of masters
• Number of slaves

⚡ Pipelining and Burst Transfers

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Two major AHB performance features are:

• Pipelined transfers
• Burst transfers

Pipelined Operation

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AHB divides communication into two overlapping phases:

1. Address phase
2. Data phase

This allows one transfer’s data phase to execute while the next transfer’s address phase begins simultaneously.

Conceptually:

• Cycle N → Transfer A address
• Cycle N+1 → Transfer A data + Transfer B address
• Cycle N+2 → Transfer B data + Transfer C address

This overlap significantly improves bus utilization and throughput.

Burst Transfers

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AHB also supports burst transactions.

Instead of transmitting each address individually, a master provides:

• A starting address
• Burst length
• Transfer type

Subsequent addresses are automatically incremented or wrapped.

Burst mode is especially valuable for:

• DMA transfers
• Cache line fills
• Sequential memory access
• High-throughput streaming

By reducing control overhead, burst transfers improve efficiency and reduce latency.

🧩 Why High-Speed Components Use AHB

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The CPU core requires extremely fast access to:

• Instruction memory
• SRAM
• DMA buffers
• Peripheral registers

To avoid becoming performance bottlenecks, these subsystems typically communicate through AHB.

For example, in ARM Cortex-M systems:

• Flash interfaces often sit on AHB
• SRAM connects directly to AHB
• DMA engines operate as AHB masters

This architecture enables efficient parallel operation between processing and data movement.

🔌 Understanding the APB Bus

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APB stands for Advanced Peripheral Bus.

Unlike AHB, APB prioritizes:

• Simplicity
• Low power consumption
• Reduced implementation cost

It is designed specifically for low-bandwidth peripherals that do not require high-speed transfers.

Typical APB peripherals include:

• UART
• GPIO
• Timers
• Watchdog controllers
• I2C controllers
• SPI controllers

🛠️ APB Design Characteristics

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Simplified Interface

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Compared with AHB, APB has a much simpler signal structure.

Core APB signals include:

• PCLK
• PRESETn
• PADDR
• PSELx
• PENABLE
• PWRITE
• PWDATA
• PRDATA

This reduced complexity minimizes:

• Silicon area
• Verification overhead
• Power consumption

Non-Pipelined Transfers

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APB intentionally avoids pipelining.

Each transfer executes through two sequential phases:

1. SETUP
2. ENABLE

A new transaction cannot begin until the previous transaction fully completes.

As a result:

• Transfers require at least two clock cycles
• Address and data phases never overlap
• Timing becomes highly deterministic

This simplicity is ideal for register-oriented peripherals.

No Burst Support

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APB only supports single-address transfers.

Every read or write operation requires a separate transaction.

For example, writing three consecutive registers requires:

• Three independent SETUP phases
• Three ENABLE phases
• Three complete transactions

Although less efficient than AHB, this dramatically simplifies peripheral design.

🌉 The AHB-to-APB Bridge

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Inside most ARM-based MCUs, AHB acts as the high-speed backbone bus while APB serves as a lower-speed peripheral bus.

These buses operate very differently:

AHB	APB
High-speed	Low-speed
Pipelined	Non-pipelined
Burst capable	Single transfer only
Multi-master	Single-master
Complex arbitration	Simple interface

Directly connecting them would create severe performance problems.

To solve this, systems use an AHB-to-APB Bridge.

🔄 How the Bridge Works

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The bridge serves two roles simultaneously:

• AHB slave
• APB master

It performs:

• Protocol conversion
• Address decoding
• Timing adaptation
• Clock-domain synchronization

Signal Translation

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The bridge receives AHB transactions and converts them into APB-compliant operations.

This includes generating:

• PSELx
• PENABLE
• APB timing sequences

for the target peripheral.

Preventing AHB Stalls

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One of the bridge’s most important functions is preventing slow APB devices from blocking high-speed AHB traffic.

Without the bridge:

• CPU and DMA transfers could stall waiting for slow peripherals
• Overall system throughput would collapse

The bridge isolates APB latency from the main system interconnect.

Clock Domain Crossing

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In many MCUs, APB operates at a lower clock frequency than AHB.

For example:

• AHB may run at 100+ MHz
• APB may run at 25 MHz or lower

The bridge safely handles synchronization between these clock domains.

🏗️ AHB and APB Workflow Inside an MCU

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A typical MCU transaction involving APB peripherals follows this flow:

1. Address Decode

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The CPU initiates an AHB transaction.

The address decoder determines whether the target belongs to:

• SRAM
• Flash
• AHB peripherals
• APB peripherals

2. Bridge Conversion

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If the address targets an APB peripheral:

• The AHB-to-APB bridge intercepts the request
• The transaction is converted into APB format

3. Peripheral Response

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The APB peripheral executes the operation.

The response then propagates back:

• Through the bridge
• Onto the AHB bus
• Back to the requesting master

🧠 Dedicated AHB Implementations in STM32 Systems

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In ARM Cortex-M architectures such as STM32, several dedicated buses are implemented using AHB principles.

Common examples include:

ICode Bus

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Used for fetching instruction code from Flash memory.

DCode Bus

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Used for reading constants and data stored in Flash.

System Bus

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Used for accessing SRAM and peripheral registers.

DMA Bus

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Used by DMA controllers for autonomous data movement.

These are specialized implementations built on top of the AHB protocol model.

Whenever these buses access APB peripherals, transactions pass through the AHB-to-APB bridge.

📊 AHB vs APB Quick Comparison

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Feature	AHB	APB
Full Name	Advanced High-performance Bus	Advanced Peripheral Bus
Primary Role	High-speed backbone bus	Low-speed peripheral bus
Performance	High throughput	Low bandwidth
Transfer Type	Pipelined	Non-pipelined
Burst Support	Yes	No
Arbitration	Multi-master supported	Single-master
Complexity	High	Low
Typical Devices	CPU, SRAM, DMA, Flash	UART, GPIO, Timers
Power Consumption	Higher	Lower

🧾 Conclusion

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AHB and APB form the foundation of communication inside ARM-based microcontrollers and SoCs.

At a high level:

• AHB provides high-performance communication for bandwidth-intensive components
• APB provides a lightweight, low-power interface for simple peripherals
• The AHB-to-APB Bridge connects both worlds efficiently

Understanding how these buses interact provides valuable insight into:

• MCU internal architecture
• Peripheral latency
• DMA behavior
• System-level performance optimization

For embedded developers working with STM32, Cortex-M, or ARM-based SoCs, mastering AHB and APB concepts is essential for understanding how data actually moves through the system.