Alibaba XuanTie C950 RISC-V CPU: 5nm, 64 Cores and LLM Inference
Alibaba’s XuanTie C950 represents a major step in the evolution of RISC-V from embedded and specialized workloads toward high-performance general-purpose and server computing.
On August 19, Alibaba’s DAMO Academy announced that the flagship RISC-V processor had achieved native support for the Qwen 3.8-27B model. The demonstration reportedly ran the 27-billion-parameter large language model entirely on the CPU, without GPU assistance or binary translation, while reaching approximately 30 tokens per second during decoding.
Alibaba also announced broad software ecosystem support for the C950, spanning more than 10 operating systems—including Android 16, Linux, openEuler, and openKylin—and more than 6,500 middleware components.
Built on TSMC’s 5nm process, the C950 combines a 64-core design, a 3.2GHz clock speed, vector processing, and a dedicated matrix engine. Together, these capabilities position the processor as an ambitious attempt to demonstrate that RISC-V can scale beyond traditional embedded applications into demanding AI and server workloads.
🚀 XuanTie C950 Hardware Specifications #
The C950 is designed around a high-performance RISC-V architecture with substantial parallel compute capability.
| Specification | XuanTie C950 |
|---|---|
| Process Node | TSMC 5nm |
| Core Count | 64 cores |
| Maximum Clock Speed | 3.2 GHz |
| SPECint2006 | >70 points |
| AI Compute | Up to 8 TFLOPS per core, FP8 |
| Vector Extension | RVV 1.0 |
| Matrix Engine | AME v0.5 |
| LLM Support | 100B+ parameter-class models |
The combination of 5nm fabrication, 64 CPU cores, and a 3.2GHz operating frequency gives the C950 a configuration aimed at substantially higher performance than conventional RISC-V processors.
Its reported SPECint2006 score above 70 points is particularly significant within the RISC-V ecosystem. While benchmark results alone do not establish application-level performance, the figure indicates that Alibaba is targeting competitive general-purpose compute rather than focusing exclusively on embedded workloads.
A server-oriented RISC-V architecture #
The C950’s design reflects a shift in RISC-V processor ambitions. Instead of optimizing primarily for microcontrollers, edge devices, or specialized control workloads, Alibaba is targeting compute-intensive environments where memory bandwidth, vector execution, multicore scaling, and software compatibility are critical.
The 64-core configuration also provides the parallelism required for server applications and CPU-based AI inference.
🧠 Native LLM Inference Without a GPU #
The C950’s most notable demonstration is its ability to execute a large language model directly on the CPU.
Alibaba reported that the processor can run the Qwen 3.8-27B model natively at approximately 30 tokens per second during decoding, without relying on a discrete GPU or binary translation layer.
This demonstration is important because LLM inference typically places significant demands on matrix multiplication, vector operations, memory bandwidth, and numerical throughput.
The C950 addresses these workloads through a combination of general-purpose CPU cores and dedicated compute engines.
Vector Engine: RVV 1.0 #
The Vector Engine implements the RISC-V Vector Extension 1.0 (RVV 1.0), enabling the processor to execute operations across multiple data elements within a single instruction.
For Transformer-based workloads, vector execution can accelerate operations involved in attention, activation functions, normalization, and other numerical kernels.
Matrix Engine: AME v0.5 #
The C950 also integrates an AME v0.5 matrix engine designed to accelerate matrix operations.
Matrix multiplication is one of the dominant computational primitives in neural-network inference. A dedicated matrix engine allows the processor to execute these operations more efficiently than relying exclusively on conventional scalar CPU execution.
Together, the vector and matrix engines give the C950 an architecture that combines general-purpose RISC-V processing with specialized AI acceleration.
🧩 Software Ecosystem Adaptation #
Hardware capability alone is insufficient for a new CPU architecture to gain traction. Operating-system support, middleware compatibility, compilers, libraries, and AI frameworks all determine how easily developers can deploy applications.
Alibaba’s reported C950 ecosystem work addresses this software layer across multiple levels.
Operating system support #
The C950 ecosystem reportedly includes support for more than 10 operating systems and distributions, including:
- Android 16
- Linux
- openEuler
- openKylin
On Android 16, Alibaba reported more than 68,000 CTS/VTS tests and compliance with RVA23 requirements. C950 support has also been integrated into the Linux ecosystem, while compatibility has been validated on openEuler and openKylin.
This level of operating-system validation is important because it moves the platform beyond a silicon demonstration toward practical system deployment.
Middleware compatibility #
More than 6,500 middleware components have reportedly been verified for the C950 platform.
The supported software stack includes widely deployed server components such as:
- MySQL
- Redis
- Nginx
- Database infrastructure
- Server applications
- Common middleware packages
Broad middleware compatibility reduces the amount of architecture-specific engineering required when porting existing applications to RISC-V.
AI framework and model support #
The C950 platform also targets modern AI workloads, with native support announced for Qwen and DeepSeek model families.
Additional work is being carried out across AI software frameworks such as PyTorch and TensorFlow, which are critical for broader machine-learning deployment.
The objective is to make RISC-V a usable target throughout the AI software stack rather than requiring developers to build isolated architecture-specific implementations.
🏗️ Alibaba’s Broader Semiconductor Strategy #
The XuanTie C950 is part of Alibaba T-Head’s broader processor and accelerator portfolio.
| Chip | Target Positioning | Architecture |
|---|---|---|
| XuanTie C950 | Server CPU | RISC-V |
| Yitian 710 | Cloud Server CPU | ARM |
| Hanguang 800 | AI Inference Accelerator | Custom |
| Zhenwu 810E | AI Training Accelerator | Custom |
This portfolio spans multiple processor architectures and workload categories.
The Yitian 710 provides an ARM-based cloud CPU platform, while the XuanTie C950 expands Alibaba’s options into high-performance RISC-V computing. Dedicated accelerators such as Hanguang 800 and Zhenwu 810E address specialized AI inference and training workloads.
RISC-V as a third server architecture #
RISC-V’s open instruction-set architecture gives chip designers greater control over the processor ecosystem and enables customization at the ISA and hardware level.
For Alibaba, developing a capable RISC-V server processor creates another architectural option alongside established ARM and x86 platforms.
The significance therefore extends beyond a single CPU. A mature C950 ecosystem could provide Alibaba with greater flexibility across cloud infrastructure, edge systems, and specialized computing platforms.
⚙️ Remaining Challenges for the C950 #
Despite its technical progress, the XuanTie C950 still faces several challenges before RISC-V can establish a broad presence in high-performance server computing.
Manufacturing and volume production #
Advanced-node silicon requires more than a successful tape-out. Moving toward high-volume production requires consistent yields, competitive manufacturing costs, reliable packaging, and sufficient access to advanced foundry capacity.
The transition from engineering samples to large-scale production will therefore be a critical validation point for the platform.
Commercial adoption #
Technical capability does not automatically translate into widespread deployment.
Beyond Alibaba’s own infrastructure, the C950 will need to attract cloud providers, enterprise customers, system vendors, and developers. These customers typically evaluate not only CPU performance but also total cost of ownership, software compatibility, support lifecycles, and migration complexity.
Long-term ecosystem maturity #
RISC-V has made substantial progress, but x86 and ARM benefit from decades of compiler optimization, operating-system integration, developer tooling, commercial software support, and application-level tuning.
Closing that ecosystem gap requires sustained investment across hardware, firmware, operating systems, toolchains, libraries, and application software.
🌐 RISC-V Moves Toward High-Performance Computing #
The XuanTie C950 illustrates how far RISC-V processor development has progressed.
A 64-core, 3.2GHz processor fabricated on a 5nm process and equipped with vector and matrix acceleration represents a fundamentally different class of RISC-V hardware from the microcontrollers and embedded processors that historically dominated the ecosystem.
More importantly, native execution of a 27-billion-parameter LLM demonstrates that RISC-V can be engineered for modern AI workloads rather than being limited to conventional CPU applications.
The remaining question is no longer whether RISC-V can scale technically, but how effectively platforms such as the XuanTie C950 can translate that capability into reliable mass production, broad commercial adoption, and a mature software ecosystem.