AMD Zen 7 and Zen 8 Roadmap: EPYC Florence Adds DDR6 and ACE
AMD has officially outlined its next-generation Zen 7 and Zen 8 CPU architectures, extending the company’s EPYC server roadmap through 2030. Zen 7 is scheduled to debut in the 7th-generation EPYC “Florence” platform in 2028, followed by Zen 8 and the 8th-generation EPYC “Ravenna” family in 2030.
The roadmap introduces several major changes for AMD’s future data center CPUs, including next-generation process technology, DDR6-class memory support, advanced MRDIMM and LPDDR memory configurations, and the introduction of ACE AI compute extensions.
AMD also updated its long-term Instinct accelerator roadmap, positioning the upcoming MI500 and MI600 generations alongside future EPYC architectures and rack-scale AI systems.
🚀 AMD Extends the EPYC Roadmap Through 2030 #
AMD disclosed its Zen 7 and Zen 8 roadmap during Advancing AI 2026, where the company presented a longer-term strategy covering CPUs, GPUs, rack-scale systems, and AI software.
The roadmap follows the recently introduced Zen 6-based EPYC 9006 series, which targets cloud computing, enterprise infrastructure, HPC, AI workloads, and general-purpose data center deployments.
The next two generations are positioned as follows:
- 2028 — Zen 7 / EPYC Florence: 7th-generation EPYC server processors.
- 2030 — Zen 8 / EPYC Ravenna: 8th-generation EPYC server processors.
While AMD has disclosed the architectural direction of both generations, detailed specifications for Zen 8 remain limited. Final configurations, performance targets, and product segmentation are expected to evolve as development progresses.
🧠 Zen 7 Introduces DDR6 and ACE AI Extensions #
The most substantial technical information currently available concerns Zen 7 and EPYC Florence.
AMD plans to continue offering both conventional Zen 7 cores and density-focused Zen 7c variants, allowing Florence to target different combinations of compute density, performance, and infrastructure efficiency.
Next-Generation Process Technology #
EPYC Florence is expected to use a process node in the sub-2nm class, although AMD has not yet finalized or publicly identified the exact manufacturing technology.
Moving to a more advanced process node should provide additional transistor density and efficiency headroom for higher-core-count server designs, while also creating room for larger caches, memory controllers, and specialized acceleration features.
DDR6 and Advanced Memory Support #
Florence will support next-generation memory technologies including DDR6, alongside future MRDIMM and LPDDR configurations.
The increased bandwidth of these memory technologies is particularly important for workloads where CPU throughput is constrained by memory access rather than arithmetic performance. AI preprocessing, large-scale data analytics, HPC, virtualization, and memory-intensive enterprise workloads can all benefit from higher memory bandwidth.
For high-core-count EPYC systems, memory subsystem scaling will become increasingly important as CPU compute density continues to rise.
ACE AI Compute Extensions #
Another major addition is ACE, which AMD identifies as an AI compute extension associated with the broader x86 EAG initiative.
ACE is intended to provide standardized matrix acceleration capabilities within the x86 ecosystem, with Intel and AMD participating in the development of a common interface for AI-oriented computation.
A standardized CPU-side AI acceleration interface could reduce software adaptation requirements and provide developers with a more consistent mechanism for targeting AI workloads across future x86 processors.
This is particularly relevant as more AI workloads move beyond dedicated accelerators and require CPU-side inference, preprocessing, orchestration, and agent execution.
🔌 EPYC Florence Retains SP7 and SP8 Platform Segmentation #
AMD plans to continue the SP7 and SP8 platform strategy with Zen 7.
The SP7 configuration will emphasize maximum compute density and raw performance, targeting environments where the highest possible CPU throughput per socket or rack is the primary requirement.
The SP8 platform will instead emphasize system-level efficiency and performance-per-dollar, making it better suited to cost-sensitive cloud deployments and large-scale enterprise infrastructure.
Maintaining these differentiated platforms allows AMD to address substantially different data center workloads without forcing every customer into the same CPU, memory, and I/O configuration.
Florence is also planned as the host processor for AMD’s next-generation AI rack architecture, extending EPYC’s role from conventional server CPU into the broader rack-scale AI platform.
🏗️ Ferrara and Fidenza Extend AMD’s Rack-Scale Strategy #
AMD’s future roadmap also identifies Ferrara as a next-generation AI rack platform using EPYC Florence as its host CPU.
The associated intelligent sandbox platform, Fidenza, is designed around performance-per-watt optimization for large-scale AI deployments.
This reflects AMD’s broader shift toward vertically integrated AI infrastructure. Rather than treating the CPU, accelerator, networking, memory, and software layers as independent products, AMD is increasingly positioning EPYC as part of complete rack-scale computing systems.
For cloud providers and enterprises, this approach can improve system-level optimization by allowing CPU resources, AI accelerators, memory, and interconnects to be tuned as a unified platform.
🔭 Zen 8 and EPYC Ravenna Remain a Longer-Term Target #
AMD’s Zen 8 architecture is scheduled for 2030 and will underpin the 8th-generation EPYC Ravenna family.
At this stage, AMD has not disclosed detailed core configurations, cache structures, process technology, memory bandwidth, or performance targets for Ravenna.
The limited information is consistent with its position on the long-term roadmap: the architecture remains several years from commercial deployment, leaving substantial room for changes before final silicon is announced.
The significance of Zen 8 therefore lies primarily in AMD’s continued commitment to a predictable multi-generation EPYC cadence.
⚡ AMD Updates the Instinct GPU Roadmap #
AMD simultaneously provided additional visibility into its future Instinct accelerator roadmap, aligning upcoming GPU generations with future EPYC server platforms.
MI500 Series #
The Instinct MI500 series is scheduled for 2027 and is expected to transition to the CDNA 6 architecture.
Key roadmap features include:
- HBM4E high-bandwidth memory.
- Support for copper and optical interconnects.
- Rack-scale integration targeting next-generation AI infrastructure.
- Competitive positioning against NVIDIA’s Rubin Ultra platform and its associated Kyber rack architecture.
The MI500 generation is intended to increase AMD’s competitiveness in large-scale AI training and inference, where memory bandwidth, accelerator-to-accelerator communication, and rack-level networking increasingly determine system performance.
MI600 Series #
The MI600 series is planned for 2028 and will introduce another generation of AMD’s CDNA architecture.
AMD currently positions MI600 alongside the future Zen 7 EPYC Florence platform and the Ferrara rack architecture.
The company also identifies NVIDIA’s future Feynman architecture as a competitive target, illustrating how AMD is planning its accelerator roadmap against NVIDIA’s multi-generation product cadence rather than competing only against currently available hardware.
📊 AMD’s CPU and GPU Roadmap Is Becoming More Integrated #
The most important aspect of AMD’s roadmap is not any individual specification but the increasing integration between its CPU, GPU, memory, and rack-scale product lines.
The roadmap can be summarized as:
| Year | CPU Platform | GPU Platform | Rack-Scale Direction |
|---|---|---|---|
| 2027 | Zen 6 EPYC | Instinct MI500 / CDNA 6 | Next-generation AI infrastructure |
| 2028 | Zen 7 EPYC Florence | Instinct MI600 | Ferrara-class AI systems |
| 2030 | Zen 8 EPYC Ravenna | Future Instinct generation | Future rack-scale platforms |
This strategy allows AMD to coordinate CPU and accelerator development around increasingly heterogeneous AI workloads.
As data centers evolve toward AI-centric architectures, CPU performance alone becomes less important than the efficiency of the complete compute system. Memory bandwidth, accelerator interconnects, rack-level power efficiency, and software compatibility increasingly determine the total cost and throughput of AI infrastructure.
🎯 What Zen 7 Means for Future Data Centers #
Zen 7’s combination of next-generation process technology, DDR6-class memory, MRDIMM support, and ACE AI extensions indicates that AMD is adapting EPYC around the changing role of CPUs in AI infrastructure.
Future server CPUs will increasingly serve as orchestration engines for heterogeneous systems, handling data preparation, inference control, agent execution, storage and networking coordination, and workloads that do not justify dedicated accelerator resources.
ACE could become particularly relevant in this environment by giving future x86 processors standardized capabilities for matrix-oriented AI computation.
At the same time, higher-bandwidth DDR6 and advanced memory modules should help prevent CPU performance from being constrained by the memory subsystem as core counts and accelerator connectivity continue to scale.
📝 Roadmap Status and Final Outlook #
AMD’s Zen 7 and Zen 8 announcements provide a long-range view of its data center strategy, but the specifications should be treated as roadmap targets rather than final product commitments.
EPYC Florence is currently positioned for 2028, while EPYC Ravenna is planned for 2030. Process selection, core counts, cache configurations, memory standards, interconnects, and launch schedules can all change before commercial products reach the market.
Nevertheless, the direction is clear. AMD is building future EPYC generations around increasingly high-bandwidth memory, specialized AI acceleration, heterogeneous computing, and tighter integration with Instinct GPUs and rack-scale systems.
If the roadmap remains on schedule, Zen 7 Florence and Zen 8 Ravenna will extend AMD’s EPYC strategy well into the next decade, while the parallel MI500 and MI600 accelerator generations will give AMD a coordinated CPU-GPU platform for increasingly AI-centric data centers.