Intel Diamond Rapids Xeon 7 Leak Reveals 32 Cores and 240MB L3
An early engineering sample of Intel’s next-generation Diamond Rapids Xeon 7 processor has surfaced on an Oakstream reference platform, providing an early look at Intel’s upcoming data center CPU architecture.
The engineering sample reportedly contains 32 cores, 64MB of L2 cache, and 240MB of L3 cache, while operating at an unusually low 1.1 GHz base frequency. As a validation-stage processor, the low clock speed should not be interpreted as representative of final production performance.
More importantly, the sample confirms continued development of Intel’s 18A-P process technology and provides an early indication of the cache configuration Intel is targeting for Diamond Rapids.
The broader Xeon 7 family is expected to scale substantially beyond this configuration, with Diamond Rapids reportedly targeting up to 192 cores, PCIe Gen 6 connectivity, and 16-channel memory support.
🔬 Diamond Rapids Engineering Sample Surfaces #
The leaked processor is identified as an early Diamond Rapids Xeon 7 engineering sample installed on an Intel Oakstream reference platform using the Johnson City evaluation board.
Hardware-detection databases have exposed several characteristics of the sample:
| Specification | Diamond Rapids ES |
|---|---|
| Architecture | Diamond Rapids |
| CPU Family | Xeon 7 |
| Process Node | Intel 18A-P |
| Cores | 32 |
| Base Clock | 1.1 GHz |
| L2 Cache | 64MB |
| L3 Cache | 240MB |
| Platform | Oakstream |
| Reference Board | Johnson City |
The 1.1 GHz operating frequency is particularly important to interpret correctly.
Engineering samples used for early validation frequently operate at reduced clocks while Intel verifies silicon functionality, power behavior, firmware, memory interfaces, and platform compatibility. Consequently, this frequency provides little useful information about the final performance envelope.
32 cores paired with 240MB of L3 #
The cache configuration is more revealing.
A 32-core processor carrying 240MB of L3 cache places Diamond Rapids in a competitive position against other high-cache server processors.
For comparison, the supplied data indicates that Intel’s Granite Rapids Xeon 6730P can reach 288MB of cache, while AMD’s 32-core EPYC 9005-class processors can reach up to 256MB of L3 cache.
Diamond Rapids is also expected to introduce additional configurations targeting workloads where cache capacity is a major performance factor.
⚙️ Intel 18A-P Process Technology #
The engineering sample also provides an early hardware-level indication that Intel’s 18A-P process is progressing toward production deployment.
18A-P is positioned as an enhanced derivative of Intel’s 18A manufacturing technology and is being developed for subsequent generations of high-performance processors.
According to Intel’s disclosed process metrics, 18A-P targets approximately 9% higher performance at equivalent power, or approximately 18% lower power at equivalent performance, based on standard ARM core sub-module testing.
These figures are process-level characteristics rather than direct predictions for Diamond Rapids server CPU performance.
GAA and backside power delivery #
18A-P retains the core technologies introduced with Intel 18A, including:
- Gate-All-Around transistor architecture
- Backside power delivery
- PowerVia technology
- Existing 18A-compatible design rules and workflows
Maintaining design-rule compatibility with the base 18A process can reduce the engineering overhead associated with migrating existing intellectual property and design flows to the enhanced node.
For a large server CPU, this compatibility can be particularly valuable because the processor integrates substantial amounts of compute, cache, I/O, and interconnect logic.
🔋 PowerVia and Power Boost Architecture #
Intel 18A-P also incorporates an enhanced power-delivery approach referred to as Power Boost.
The technology is designed around a dual-contact transistor architecture for NMOS and PMOS devices, enabled by backside power delivery through PowerVia.
The objective is to improve electrical efficiency and performance density without requiring a proportional increase in die area.
Intel is also targeting high-density transistor-cell implementations, with reported options around 160nm and 180nm cell configurations.
Why backside power matters for server CPUs #
Backside power delivery separates portions of the power-distribution network from conventional front-side signal routing.
For high-performance CPUs, this can help reduce power-delivery congestion and improve the electrical environment available to logic transistors.
The potential benefits become increasingly relevant as core counts, cache capacity, and operating power continue to increase.
However, the ultimate system-level advantage depends on how Intel implements these process capabilities in the final Diamond Rapids products.
🖥️ Oakstream Platform Targets High-Power Xeon Configurations #
The Johnson City reference platform reportedly supports processors with TDPs reaching approximately 650W.
Diamond Rapids uses the Oakstream platform with an LGA 9324 socket, reflecting the substantial electrical and thermal requirements of Intel’s upcoming high-core-count Xeon processors.
A platform operating at this power level requires significantly more sophisticated:
- Voltage regulation
- Socket power delivery
- Memory power management
- Cooling infrastructure
- Firmware-level power controls
- Rack-level thermal planning
The platform therefore provides an early indication that Intel is preparing Diamond Rapids for increasingly dense server configurations.
🚀 Diamond Rapids Targets Up to 192 Cores #
The leaked 32-core sample represents only one configuration within the broader Diamond Rapids family.
The platform is expected to scale to as many as 192 cores, alongside support for:
- PCIe Gen 6
- 16-channel memory
- High-capacity cache configurations
- High-power server platforms
This puts Diamond Rapids directly into the next generation of high-density data center CPU competition.
Intel’s strategy is increasingly centered on combining higher core counts with process-node improvements, memory bandwidth, cache capacity, and platform-level I/O.
For workloads such as AI orchestration, virtualization, analytics, and high-density cloud infrastructure, these characteristics can be as important as raw single-threaded performance.
⚔️ Intel Diamond Rapids vs. AMD EPYC Venice #
Diamond Rapids will enter a market where AMD’s next-generation EPYC Venice and Verano processors are already establishing the competitive baseline.
AMD’s upcoming Zen 6 server products are built using TSMC’s 2nm process technology, with flagship configurations reportedly reaching up to 256 cores.
The core-count comparison therefore favors AMD on the highest-density configurations.
| Platform | Architecture | Process | Maximum Reported Cores | Key Platform Features |
|---|---|---|---|---|
| Intel Diamond Rapids | Diamond Rapids | 18A-P | Up to 192 | PCIe Gen 6, 16-channel memory |
| AMD EPYC Venice | Zen 6 | TSMC 2nm | Up to 256 | High core density, PCIe Gen 6 |
| AMD Verano | Zen 6 | TSMC 2nm | Configuration dependent | Low-power server focus |
Core count alone, however, does not determine server CPU competitiveness.
Actual performance will depend on architecture, IPC, memory bandwidth, cache behavior, frequency, power efficiency, accelerator integration, software optimization, and workload characteristics.
The efficiency battle will be critical #
AMD has increasingly emphasized performance-per-watt and total system efficiency across its EPYC roadmap.
Intel’s 18A-P process therefore represents more than a simple node transition.
If Diamond Rapids can translate Intel’s transistor and backside-power innovations into meaningful efficiency improvements at high core counts, it could narrow the gap against AMD in workloads where power and rack density are major procurement considerations.
📊 Data Center CPU Competition Enters Another Phase #
The timing of Diamond Rapids is particularly significant because data center CPU demand is changing alongside the rapid expansion of AI infrastructure.
AI clusters still require substantial conventional CPU resources for:
- Data preprocessing
- Storage and networking orchestration
- Model serving
- Agent execution
- Memory management
- Scheduling
- Control-plane workloads
The growth of agentic AI may further increase CPU demand because autonomous software systems can generate large numbers of concurrent tool calls, retrieval operations, service requests, and control tasks.
This creates opportunities for both Intel and AMD to sell high-core-count CPUs alongside AI accelerators.
🧮 Intel’s Position in the Server CPU Market #
AMD has continued gaining server CPU market share, and the competitive pressure on Intel remains significant.
The supplied market outlook indicates that AMD expects its data center CPU revenue share to exceed 50% by the end of 2026 while substantially expanding the overall scale of its data center CPU business.
That places additional importance on Diamond Rapids.
Intel must compete not only through peak performance but also through total cost of ownership, platform compatibility, software ecosystem support, memory capacity, networking integration, and energy efficiency.
The final Diamond Rapids product stack will therefore be evaluated at the system level rather than solely by specifications such as core count.
🗓️ Diamond Rapids Launch Timeline #
Diamond Rapids is expected to officially launch in 2027, following the current generation of Xeon processors.
Intel is subsequently expected to introduce the Coral Rapids family, which is reportedly planned to restore support for Simultaneous Multithreading (SMT).
This creates a relatively clear progression for Intel’s server CPU roadmap:
- Diamond Rapids: Next-generation Xeon 7 architecture built on 18A-P.
- Coral Rapids: Subsequent generation expected to reintroduce SMT.
- Continued expansion toward higher-density AI and general-purpose server workloads.
The appearance of an early Diamond Rapids engineering sample suggests that Intel’s development program is sufficiently mature for silicon validation on production-oriented reference platforms.
🔍 What the 32-Core Sample Reveals #
The most important information from this engineering sample is not the 1.1 GHz clock speed.
Instead, three characteristics stand out:
First, cache remains a major architectural focus. A 32-core configuration with 240MB of L3 demonstrates Intel’s willingness to maintain a very large cache footprint for high-throughput server workloads.
Second, Intel 18A-P is moving into practical silicon validation. The appearance of Diamond Rapids silicon on an Oakstream platform provides tangible evidence that the enhanced process technology is being integrated into future server products.
Third, platform power requirements are increasing. A reference design supporting up to 650W indicates that Intel is preparing for server processors where power delivery and cooling will be central design constraints.
🚀 Diamond Rapids Sets Up Intel’s Next Server CPU Battle #
The early Diamond Rapids Xeon 7 sample provides a useful first look at Intel’s next major data center CPU generation.
The reported 32-core configuration, 240MB of L3 cache, 18A-P process technology, PCIe Gen 6 support, and high-power Oakstream platform point toward a server architecture designed for substantially greater compute and I/O density.
At the same time, AMD’s Zen 6 EPYC roadmap is targeting up to 256 cores on TSMC’s 2nm process, raising the competitive bar for Intel’s next generation.
The final outcome will depend on far more than core counts. Frequency scaling, IPC, memory bandwidth, cache efficiency, power consumption, platform cost, and workload-specific performance will determine whether Diamond Rapids can regain meaningful ground in the data center CPU market.
For now, the appearance of a functioning 18A-P Diamond Rapids engineering sample marks an important milestone: Intel’s next Xeon generation is moving from roadmap claims toward real silicon validation.