I2C Bus Explained: The Two-Wire Protocol for Embedded Systems

I2C Bus Explained: The Two-Wire Protocol for Embedded Systems

The I2C (Inter-Integrated Circuit) bus is one of the most widely used communication protocols in embedded systems. Designed for simplicity and efficiency, it allows a microcontroller to communicate with multiple peripherals using just two wires.

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⚡ Physical Topology: Open-Drain Simplicity

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I2C minimizes wiring by using a shared bus architecture:

• SDA (Serial Data Line): Transfers data
• SCL (Serial Clock Line): Synchronizes communication
• Pull-up Resistors: Required to define logic HIGH (open-drain cannot drive HIGH)

Key Characteristics

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Feature	Description
Open-Drain Design	Devices can only pull lines LOW; HIGH is via pull-ups
Bus Capacitance	Limited to 400pF (short distance communication)
Addressing	7-bit (common) or 10-bit device addressing

Without proper pull-ups, the bus will fail—signals will never reach a valid HIGH level.

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🔄 Signaling Rules: START, STOP, and Data Validity

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I2C communication is defined by how SDA behaves relative to SCL:

• Data Validity: SDA must remain stable when SCL is HIGH
• START Condition: SDA transitions HIGH → LOW while SCL is HIGH
• STOP Condition: SDA transitions LOW → HIGH while SCL is HIGH

These transitions define the boundaries of every transaction.

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📦 Data Frame Structure: Bytes + ACK

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All I2C data transfers follow a strict structure:

1. Address Frame

   • 7-bit slave address
   • 1-bit R/W flag (0 = Write, 1 = Read)

2. Data Bytes

   • Transmitted MSB first
   • Always 8 bits per byte

3. ACK/NACK Bit (9th Clock)

   • ACK (0): Receiver confirms success
   • NACK (1): Error, buffer full, or end of read

Key Insight

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Every byte requires acknowledgment—this ensures reliable communication even on noisy lines.

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🔁 Common Transaction Patterns

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📝 Master Write

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• Master sends START
• Sends address + Write bit
• Slave ACKs
• Master sends data bytes

📖 Master Read

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• Master sends START
• Sends address + Read bit
• Slave transmits data
• Master ACKs each byte (NACK on last byte)

🔄 Combined Format (Repeated START)

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Used for register access:

• Write register address
• Issue Repeated START
• Switch to Read mode

Advantage: Prevents bus release in multi-master systems and improves efficiency.

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🚀 Speed Modes

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Mode	Max Speed	Typical Use
Standard Mode	100 kbit/s	Basic sensors
Fast Mode	400 kbit/s	Displays, modern peripherals
High-Speed Mode	3.4 Mbit/s	High-performance devices

Higher speeds require tighter control over signal integrity and pull-up sizing.

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🛠️ Debugging & Design Tips

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• Pull-Up Resistors Matter

  • Too large → slow rise time → signal corruption
  • Typical values:
    • 100kHz: ~4.7kΩ–10kΩ
    • 400kHz: ~2.2kΩ–4.7kΩ

• Watch Bus Capacitance

  • Long traces or cables degrade signal quality

• Avoid Address Conflicts

  • Use configurable address pins where possible

• Use Logic Analyzers

  • Essential for visualizing START/STOP and ACK behavior

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🧩 Summary

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I2C remains the go-to protocol for low-speed, short-distance communication thanks to its simplicity and flexibility. By understanding its open-drain nature, strict signaling rules, and acknowledgment system, you can design robust and efficient embedded systems.

Master the fundamentals—and most I2C bugs become predictable and easy to fix.