PCIe 6.0 and CXL 3.1 Controllers Mark Storage Breakthrough
The enterprise storage industry is entering a new performance era as PCIe 6.0 and CXL 3.1 controllers move from roadmaps into silicon.
At FMS 2026 in Santa Clara, InnoGrit showcased a CXL 3.1 controller and a PCIe 6.0 SSD controller, both of which reportedly completed tape-out during the first half of 2026. The simultaneous development of these two technologies highlights how rapidly storage architectures are adapting to AI workloads, where bandwidth, latency, memory capacity, and data movement increasingly determine system performance.
The significance extends beyond interface speeds. CXL is changing how servers think about memory expansion and pooling, while PCIe 6.0 is creating substantially more bandwidth between processors, accelerators, and storage devices.
Other major controller vendors are moving in the same direction. Marvell has introduced its Bravera SC6 PCIe 6.0 enterprise controller, while Silicon Motion has started development of PCIe Gen7 enterprise SSD controllers.
For consumers, however, the transition will take considerably longer. The first wave of PCIe 6.0 and CXL products is primarily designed for enterprise servers, AI clusters, and cloud infrastructure.
🚀 InnoGrit Brings CXL 3.1 and PCIe 6.0 to Silicon #
InnoGrit’s latest controller portfolio targets two different but increasingly interconnected bottlenecks: memory capacity and storage bandwidth.
The company’s CXL controller is designed around the CXL 3.1 specification while maintaining backward compatibility with CXL 2.0. Its primary purpose is memory expansion, allowing servers to access additional memory resources through the CXL interconnect rather than relying exclusively on conventional CPU-attached DIMM capacity.
This becomes particularly relevant in AI infrastructure, where large language models, recommendation systems, databases, and other memory-intensive workloads can rapidly exhaust local DRAM capacity.
CXL Enables Flexible Memory Expansion #
Traditional server memory configurations are constrained by the processor’s memory channels, supported DIMMs, motherboard layout, and available memory capacity.
CXL changes this architecture by allowing compatible devices to be attached through high-speed PCIe-based links while providing a memory-semantic interface.
Depending on the CXL device type and system architecture, this can enable:
- Memory expansion beyond local DRAM capacity.
- Memory pooling across multiple compute resources.
- More flexible memory allocation.
- Reduced dependence on expensive local DRAM for certain workloads.
- New tiers of memory and storage within AI servers.
InnoGrit’s approach reportedly combines CXL with NAND-based memory technologies to create a lower-cost capacity tier compared with conventional DRAM.
The key architectural advantage is flexibility rather than simply raw bandwidth. AI servers can increasingly treat memory and storage as a hierarchy of resources instead of isolated components permanently attached to individual processors.
⚡ PCIe 6.0 Doubles the Interface Bandwidth #
The second major InnoGrit development is its PCIe 6.0 SSD controller.
PCIe 6.0 increases the signaling rate to 64 GT/s per lane, effectively doubling the raw transfer rate of PCIe 5.0. A PCIe 6.0 x4 connection therefore provides substantially more bandwidth than the equivalent PCIe 5.0 interface, although actual application throughput depends on protocol overhead, controller architecture, NAND performance, and system implementation.
This additional bandwidth is particularly attractive for AI infrastructure.
Large-scale AI training and inference systems constantly move data between storage, system memory, CPUs, GPUs, and accelerator memory. As accelerator performance increases, storage increasingly becomes part of the overall data pipeline rather than simply a capacity device.
InnoGrit IG5686 Targets Enterprise AI Storage #
InnoGrit previously demonstrated its IG5686 PCIe 6.0 SSD controller, also known as Crestone, targeting enterprise, data-center, and AI workloads.
The controller supports:
- PCIe Gen6 x4.
- NVMe 2.3.
- Capacities of up to 256TB.
- Sequential read speeds of up to 28 GB/s.
- Sequential write speeds of up to 22 GB/s.
- Random read performance of up to 7 million IOPS.
- Random write performance of up to 5 million IOPS.
- SLC, MLC, TLC, and QLC NAND.
- Storage Class Memory configurations.
- NAND interface speeds of up to 4800 MT/s.
- Enterprise E1.S and E3.S form factors.
These specifications place the controller firmly in the enterprise segment rather than the consumer SSD market.
The combination of high sequential bandwidth and very high random I/O performance is particularly relevant to AI workloads, where large datasets and enormous numbers of concurrent requests can create storage bottlenecks.
🧠 CXL 3.1 Extends the Memory Hierarchy #
InnoGrit also demonstrated the IG5676, a CXL 3.1 Type-3 device controller designed for memory and storage expansion.
The controller supports XL-FLASH as Storage Class Memory and is positioned as a cost-oriented CXL storage solution with capacities of up to 2TB.
The Type-3 CXL device category is particularly important because it allows hosts to access memory resources provided by an external device. This creates an intermediate tier between conventional DRAM and traditional block storage.
For AI infrastructure, such tiers can become valuable when workloads exceed the capacity of local high-bandwidth memory or system DRAM.
Storage Moves Closer to the Compute Pipeline #
The broader industry trend is toward reducing the distance between computation and data.
Traditional architectures often follow a relatively simple hierarchy:
CPU/GPU
↓
DRAM
↓
SSD
↓
Network Storage
AI infrastructure increasingly requires a more flexible hierarchy:
GPU / Accelerator
↓
HBM
↓
DDR / CXL Memory
↓
High-Speed NVMe SSD
↓
Distributed Storage
CXL and PCIe 6.0 are important because they provide higher-bandwidth links between these layers.
This does not mean NAND will replace HBM or DRAM. Each technology occupies a different point in the hierarchy. Instead, the objective is to place the right data at the right memory or storage tier based on latency, capacity, bandwidth, and cost requirements.
📊 InnoGrit’s Roadmap Extends to PCIe Gen7 #
InnoGrit’s roadmap extends beyond PCIe 6.0.
The company plans to continue optimizing its PCIe Gen6 and CXL implementations through 2027, with a stated target of increasing I/O performance into the 25 million to 50 million IOPS range for large inference clusters and long-context AI workloads.
By 2028, the company plans to introduce PCIe Gen7 controllers with a target of approximately 100 million IOPS.
These numbers illustrate where enterprise storage is heading: not simply toward faster sequential transfers, but toward extremely high concurrency and low-latency data access.
However, these roadmaps should be interpreted as targets rather than guaranteed production performance. Real-world SSD performance depends on NAND media, firmware, queue depth, thermal conditions, workload characteristics, and system-level bottlenecks.
Consumer PCIe 6.0 Remains Years Away #
Despite the impressive enterprise specifications, desktop users should not expect PCIe 6.0 SSDs to become mainstream immediately.
PCIe 6.0 platforms and controllers are initially being developed around server and AI infrastructure requirements, where the cost of high-end storage can be justified by the value of the workloads.
Consumer adoption will require compatible CPUs, motherboards, SSD controllers, NAND, cooling solutions, and sufficient application demand.
As a result, mainstream consumer PCIe 6.0 SSDs are likely to arrive considerably later than their enterprise counterparts.
🔥 Marvell Bravera SC6 Targets AI Inference #
InnoGrit is not the only controller vendor moving into PCIe 6.0.
Marvell Technology has announced its Bravera SC6 PCIe 6.0 enterprise SSD controller, with customer sampling expected to begin in the fourth quarter of 2026.
The controller is designed specifically around the increasingly demanding data requirements of AI inference and cloud infrastructure.
One of its most interesting applications involves KV cache management.
Large language model inference generates substantial Key-Value cache data as context grows. Traditionally, this information resides in expensive high-bandwidth memory resources, particularly HBM attached to accelerators.
Moving selected KV-cache data to lower-cost storage tiers could potentially reduce the amount of expensive accelerator memory required for certain workloads.
Trading Some Latency for Capacity #
The concept is not about replacing HBM with NAND outright.
HBM remains dramatically faster and better suited to latency-sensitive computation. Instead, the objective is to create a hierarchy in which frequently accessed data remains close to the accelerator while less frequently accessed information can be moved to cheaper memory or storage tiers.
Marvell’s Bravera SC6 is designed to support this broader storage hierarchy.
The controller reportedly integrates:
- 12 Arm Cortex-R82 CPU cores.
- A dedicated DDR5 memory controller.
- 5MB of SRAM cache.
- PCIe 6.0 connectivity.
- Up to 28 GB/s theoretical sequential bandwidth.
- 16 NAND channels.
- NAND interface rates up to 3600 MT/s.
- Marvell’s sixth-generation NANDEdge ECC technology.
- Hardware RAID capabilities.
- AES and RSA-based security features.
The architecture reflects the changing role of enterprise SSDs. Storage controllers are becoming increasingly specialized computing components rather than simple interfaces between NAND and a host system.
🔐 Security Becomes Part of the Storage Architecture #
AI infrastructure is increasingly deployed in shared cloud and enterprise environments, making storage security just as important as bandwidth.
Modern enterprise SSD controllers therefore integrate encryption, error correction, RAID capabilities, telemetry, firmware management, and other functions directly into the controller architecture.
Marvell’s Bravera SC6 supports end-to-end encryption mechanisms including AES and RSA, helping address security requirements for cloud and enterprise deployments.
This integration is particularly important as storage becomes more tightly coupled with AI infrastructure. When storage participates directly in data pipelines and memory hierarchies, protecting that data becomes an architectural requirement rather than an optional feature.
🔮 Silicon Motion Starts PCIe Gen7 Development #
The industry is already looking beyond PCIe 6.0.
Silicon Motion announced that it has begun development of its next-generation PCIe Gen7 enterprise SSD controller architecture, with internal samples targeted for the second half of 2027.
The company has reportedly completed the architecture and feature definition phase and is now moving through active development.
PCIe 7.0 doubles the signaling rate again, reaching 128 GT/s per lane. Under an x16 configuration, the standard is designed to provide enormous aggregate bidirectional bandwidth, making it particularly attractive for AI accelerators, cloud infrastructure, networking, and other bandwidth-intensive systems.
PCIe 7.0 Is Designed for AI-Scale Infrastructure #
The progression is becoming increasingly clear:
PCIe 4.0 → PCIe 5.0 → PCIe 6.0 → PCIe 7.0
↓ ↓ ↓ ↓
Mainstream AI/Server AI/Server Next-Gen AI
↓ ↓ ↓ ↓
Higher bandwidth and lower data-movement bottlenecks
Each generation increases the amount of data that can move through the same physical lane count.
For AI systems, this is critical because accelerator compute performance is advancing faster than many traditional storage architectures can feed it.
Silicon Motion’s move toward Gen7 therefore reflects a broader industry strategy: storage must evolve alongside GPU and accelerator performance rather than remaining a secondary subsystem.
📦 Enterprise Storage Faces a NAND Supply Constraint #
One potential limitation is not interface bandwidth but NAND availability.
Silicon Motion has indicated that NAND shortages could persist through 2027, potentially affecting SSD supply and pricing.
This creates an interesting contrast.
At the controller level, PCIe bandwidth is advancing rapidly. At the media level, however, NAND production capacity and pricing remain fundamental constraints.
The result is that next-generation enterprise SSDs may offer extraordinary interface performance without necessarily becoming inexpensive.
For AI infrastructure operators, total cost of ownership will therefore depend on more than raw SSD throughput. Capacity utilization, endurance, cooling, power consumption, storage-tier placement, and workload efficiency will all influence the economic value of next-generation storage.
🏗️ The Bigger Shift: Storage Becomes Part of AI Compute #
The most important development is not simply that PCIe 6.0 SSDs are getting faster.
It is that storage is increasingly becoming an active component of AI system architecture.
Historically, storage was primarily treated as persistent capacity. Modern AI systems are changing that relationship.
CXL allows memory resources to be expanded and pooled. PCIe 6.0 provides higher-bandwidth connections to storage. Advanced controllers perform increasingly sophisticated data management and security operations. AI workloads can potentially use storage tiers for datasets, model weights, KV caches, checkpoints, and other high-volume data.
This creates a much more heterogeneous memory and storage hierarchy.
From Storage Capacity to Data Infrastructure #
The emerging architecture can be summarized as:
AI Accelerator
│
HBM
│
DDR / CXL Memory
│
PCIe 6.0 / PCIe 7.0
│
High-Speed NVMe SSD
│
Distributed Storage
The goal is not to make every layer equally fast. The goal is to minimize the cost of moving data while placing each workload at the most appropriate tier.
For large AI systems, that can have a greater economic impact than simply increasing raw SSD throughput.
🔍 The Bottom Line #
The simultaneous emergence of CXL 3.1 and PCIe 6.0 controllers represents a significant step in the evolution of high-end storage infrastructure.
InnoGrit’s latest controllers demonstrate how Chinese storage silicon vendors are moving into increasingly advanced interconnect technologies, while Marvell and Silicon Motion are pushing their own PCIe 6.0 and Gen7 enterprise roadmaps.
The immediate beneficiaries will be AI data centers, cloud providers, enterprise servers, and large-scale inference infrastructure, not desktop gamers.
For consumers, PCIe 6.0 SSDs remain a long-term prospect. The current generation of high-performance consumer systems still has substantial room to exploit PCIe 4.0 and PCIe 5.0 storage, while platform support and cost will determine when newer interfaces become practical.
The more consequential trend is architectural: AI is turning storage from a passive capacity layer into an increasingly active part of the compute pipeline.
CXL expands the memory hierarchy. PCIe 6.0 and PCIe 7.0 expand the data pipeline. Advanced SSD controllers add computation, security, and intelligent data management.
The bottleneck era is not necessarily ending everywhere—but the industry is clearly building the infrastructure required to move the bottleneck somewhere else.