SK Hynix Targets 20+ Layer HBM5 Stacks With Hybrid Bonding
SK Hynix has outlined its next-generation high-bandwidth memory packaging roadmap, showing how HBM could scale beyond the current 16-layer ceiling while remaining within the physical constraints of advanced AI accelerator packages.
At Hot Chips 2026, Jaesik Lee, Vice President of Packaging Engineering at SK Hynix America, described a roadmap that combines Advanced MR-MUF, hybrid bonding, and new thermal-management techniques to increase HBM stack density.
The key transition is expected with HBM5. While HBM4 and HBM4E will continue relying on Advanced MR-MUF, SK Hynix is targeting hybrid bonding for stacks exceeding 20 layers.
The approach addresses one of the most difficult problems in HBM scaling: increasing the number of vertically stacked DRAM dies without exceeding package height, thermal, mechanical, and manufacturing limits.
🧠 Why Higher HBM Stacks Matter for AI Accelerators #
HBM has become a critical memory subsystem for high-performance AI accelerators. GPUs and other AI processors use vertically stacked DRAM to increase capacity and bandwidth while keeping memory physically close to the compute die.
The technology relies heavily on Through-Silicon Vias (TSVs), which provide vertical electrical connections through individual DRAM dies.
Increasing the number of layers provides a straightforward path toward higher capacity within the same general package footprint, but each additional die makes the mechanical and thermal constraints more difficult to manage.
HBM Layer Scaling #
SK Hynix’s roadmap spans several HBM generations:
| Generation | Stack Configuration | Status |
|---|---|---|
| HBM3 | 8-Hi | Mass production |
| HBM3E | 8-Hi / 12-Hi | Mass production |
| HBM4 | 12-Hi / 16-Hi | 12-Hi in mass production; 16-Hi in customer qualification |
| HBM4E | 12-Hi | Sampling |
| HBM5 | 20-Hi+ | Active R&D |
The progression illustrates the industry’s shift from increasing bandwidth per die toward increasingly aggressive three-dimensional integration.
📏 The 775 µm Height Constraint Limits Conventional HBM Scaling #
One of the central packaging challenges is the approximately 775 µm total Z-height envelope used by the accelerator package.
The memory stack has to fit within the available vertical space while being mounted alongside the main logic processor in advanced 2.5D packaging architectures.
Simply adding more DRAM dies therefore is not enough. The dies themselves must become thinner, while the vertical interconnect structure must consume less space.
Two parameters become particularly important:
- DRAM die thickness
- Interconnect pitch between stacked dies
Reducing both allows additional layers to occupy approximately the same physical envelope.
The Micro-Bump Barrier #
Current HBM manufacturing techniques such as Mass Reflow Molded Underfill (MR-MUF) rely on micro-bump interconnects.
These interconnects typically operate around the 30–40 µm pitch range. As stacks approach 16 layers, further pitch reduction becomes increasingly difficult because of mechanical stress, thermal expansion, warpage, and manufacturing tolerances.
At higher stack counts, the bumps themselves consume too much vertical and lateral space.
That makes conventional micro-bump technology increasingly difficult to scale toward 20-layer and larger configurations.
🔗 Hybrid Bonding Opens the Path Beyond 16 Layers #
SK Hynix identifies hybrid bonding as the key technology for moving beyond the conventional 16-layer limit.
Instead of relying on conventional micro-bumps, hybrid bonding directly connects copper structures between adjacent dies. The elimination of conventional bump structures allows the interconnect pitch to shrink substantially while reducing the vertical space consumed by each die-to-die connection.
Micro-Bump vs. Hybrid Bonding #
| Metric | Micro-Bump / MR-MUF | Hybrid Bonding | Scaling Impact |
|---|---|---|---|
| Interconnect pitch | 30–40 µm | Below 18 µm | Higher interconnect density |
| Target stack height | Up to ~16-Hi | 20-Hi+ | Enables taller stacks |
| Die thickness | Conventional baseline | Potentially thicker die | Improved handling and reduced warpage |
| Thermal resistance | Baseline | Lower resistance | Better heat transfer |
| Bandwidth density | Standard | Higher | More throughput per footprint |
The most important benefit is not simply a smaller connection pitch. Hybrid bonding changes the physical tradeoffs governing the entire memory stack.
With less space consumed by interconnect structures, additional DRAM layers can be added without proportionally increasing package height.
HBM4 and HBM4E Stay With MR-MUF #
SK Hynix does not plan to immediately replace MR-MUF across its HBM portfolio.
HBM4 and HBM4E are expected to continue using Advanced MR-MUF, while hybrid bonding is being developed for HBM5 and later generations.
That transition gives SK Hynix additional time to address the manufacturing challenges associated with hybrid bonding, including bonding yield, copper contamination control, alignment accuracy, process complexity, and equipment costs.
🌡️ iHBM Addresses the Thermal Problem #
Adding more DRAM layers creates another fundamental problem: heat.
The outer dies in a stack have relatively direct thermal paths toward the package, while inner dies are surrounded by additional material and neighboring layers. As the stack becomes taller, heat generated inside the memory structure becomes progressively more difficult to remove.
SK Hynix is addressing this problem with iHBM, a thermal-management technology designed to provide dedicated heat-conduction paths through high-temperature regions of the memory stack.
Localized Cooling for High-Heat Regions #
Rather than treating the entire memory cube as a uniform thermal structure, iHBM targets regions where heat concentration is highest.
One example is the die-to-die PHY area, where electrical activity can produce significant localized thermal density.
The objective is to provide a more direct thermal pathway from these regions toward the package-level cooling infrastructure.
SK Hynix’s presentation indicates that the technology can reduce overall stack thermal resistance by more than 30%, helping prevent thermal throttling as HBM stacks become taller and more densely integrated.
🧩 SK Hynix Expands Packaging Compatibility With Intel EMIB #
The HBM roadmap is also expanding beyond a single advanced-packaging ecosystem.
SK Hynix demonstrated compatibility with Intel EMIB (Embedded Multi-die Interconnect Bridge) in addition to established integration approaches such as TSMC’s CoWoS.
This is strategically important because advanced packaging capacity has become a major constraint for AI accelerator production.
A Dual-Track Packaging Strategy #
TSMC’s CoWoS ecosystem is heavily utilized by major AI-chip customers, including NVIDIA, AMD, and Broadcom. Continued growth in AI accelerator demand places additional pressure on available advanced-packaging capacity.
Supporting EMIB gives SK Hynix another path for integrating HBM with logic dies.
For hyperscalers and accelerator designers, broader HBM packaging compatibility could provide greater flexibility when selecting foundry and packaging partners.
It also reduces the risk of tying future HBM deployments to a single packaging technology.
🏭 Competitive Pressure From Samsung and Micron #
SK Hynix’s packaging roadmap is also part of a broader race among the major HBM suppliers.
The company has maintained a leading position in the HBM market, but Samsung Electronics and Micron Technology continue to expand their HBM roadmaps and manufacturing capabilities.
Samsung Electronics #
Samsung is developing alternative thermal-management structures, including its Heat Path Block (HPB) approach, while also pursuing hybrid-bonding technologies for future HBM generations.
The competition is therefore moving beyond raw memory bandwidth.
Thermal performance, stack height, manufacturing yield, packaging compatibility, and power efficiency are becoming equally important differentiators.
Micron Technology #
Micron is expanding HBM production capacity while competing aggressively in the HBM3E market.
Its focus on power efficiency and manufacturing scale gives AI accelerator customers another major source for high-bandwidth memory, increasing competitive pressure on the established HBM leaders.
🚀 HBM5 Could Redefine 3D Memory Scaling #
The significance of SK Hynix’s roadmap extends beyond simply increasing HBM from 12 or 16 layers to 20 or more.
The transition to hybrid bonding represents a change in the fundamental architecture of stacked memory interconnects.
Micro-bump technology remains highly effective for current HBM generations, but its physical scaling limits become increasingly restrictive as stack heights increase. Hybrid bonding offers a way to reduce interconnect pitch, improve thermal behavior, and reclaim package space that would otherwise be consumed by conventional bumps.
At the same time, technologies such as iHBM address the thermal consequences of higher density.
The resulting roadmap can be summarized as:
HBM4 → Advanced MR-MUF → 12/16-Hi
HBM4E → Advanced MR-MUF → Higher-density optimization
HBM5 → Hybrid Bonding + Advanced Thermal Management → 20-Hi+
🔭 The HBM Scaling Ceiling Is Moving Again #
HBM scaling is increasingly constrained by packaging physics rather than simply DRAM capacity.
The approximately 775 µm package-height envelope, micro-bump pitch, thermal resistance, wafer processing, bonding yield, and mechanical reliability all interact to determine how many dies can be stacked successfully.
SK Hynix’s roadmap suggests that the industry is preparing to overcome those constraints through a combination of hybrid bonding and more sophisticated thermal engineering.
If the manufacturing challenges can be solved at production scale, HBM5 could move beyond the 16-layer boundary and make 20-layer-plus memory stacks practical for future AI accelerators.
That would give GPU and accelerator designers another major scaling dimension at a time when AI workloads continue to demand more memory capacity, bandwidth, and energy efficiency from every package.