Google’s 9th-Gen TPU May Adopt Intel’s EMIB-T Packaging
TSMC’s CoWoS platform has become a de facto packaging standard for high-performance AI accelerators and HPC processors. However, recent industry reports suggest that Google’s 9th-generation Tensor Processing Unit (TPU), reportedly codenamed Humufish, could break from that established pattern by adopting Intel’s EMIB-T advanced packaging technology.
Google has reportedly used TSMC’s CoWoS packaging across TPU generations 3 through 8. A transition to Intel’s EMIB-T would therefore represent more than a simple supplier change. It could signal a deliberate architectural decision involving power delivery, signal integrity, thermomechanical behavior, package scalability, manufacturing capacity, and supply-chain diversification.
The potential move is particularly significant because advanced packaging has become a critical component of AI accelerator design. As compute dies become larger and multi-die architectures demand increasingly dense interconnects, package-level engineering increasingly influences overall performance, power efficiency, yield, and system reliability.
🔬 Google’s Reported Shift to Intel Advanced Packaging #
TSMC’s CoWoS family has historically dominated advanced packaging for AI and HPC processors. Its widespread adoption has been driven by the ability to integrate multiple large dies with high-density interconnects while providing the electrical and mechanical infrastructure required by high-bandwidth accelerator architectures.
Google’s TPU roadmap has followed this industry trend. If the reported information is accurate, the 9th-generation Humufish TPU would be the first major break from Google’s long-running use of CoWoS beginning with the third-generation TPU.
Why the packaging decision matters #
Advanced packaging is no longer simply a back-end manufacturing consideration. For modern AI accelerators, the package directly affects several system-level characteristics:
- Die-to-die bandwidth and latency
- Signal integrity at high data rates
- Power delivery network (PDN) impedance
- Transient current response
- Thermal dissipation
- Thermomechanical stress
- Package-level manufacturing yield
- Overall package size and scalability
Consequently, migrating from one advanced packaging platform to another requires substantial validation at both the silicon and package levels.
For an accelerator operating at extremely high power densities, packaging decisions can directly influence whether the processor can sustain its intended operating frequency and workload characteristics.
⚙️ CoWoS-L vs. Intel EMIB-T #
The reported transition is particularly interesting because TSMC’s CoWoS-L and Intel’s EMIB-T approach large multi-die packages from different architectural directions.
| Architecture Feature | TSMC CoWoS-L | Intel EMIB-T |
|---|---|---|
| Interconnect Structure | Redistribution Layer (RDL) interposer combined with Embedded Local Silicon Interconnect (LSI) bridges | Embedded silicon bridges positioned at high-density die-to-die connection regions |
| Substrate Routing | High-density routing distributed across the interposer footprint | Organic substrate handles lower-density routing outside bridge regions |
| Power Delivery | Power distribution through the interposer architecture | TSV-enabled silicon bridges, integrated MIM capacitors, and dedicated ground planes |
| Scaling Strategy | Designed for very large interposer-based packages, with future scaling beyond current reticle limitations | Uses localized silicon bridges to reduce the need for a full-area silicon interposer |
| Stress Management | Large-area interposer introduces package-level thermomechanical considerations | Localized bridges can reduce some large-area interposer stress while introducing local stress-management requirements |
TSMC CoWoS-L #
CoWoS-L combines a redistribution-layer interposer with embedded silicon interconnect structures. The interposer provides a large high-density routing surface between compute dies, memory components, and other package elements.
This architecture is particularly attractive when the package requires extensive die-to-die connectivity across a large physical area. The trade-off is that a large interposer introduces additional manufacturing and thermomechanical complexity as package dimensions increase.
Intel EMIB-T #
Intel’s EMIB technology takes a more localized approach. Rather than relying on a large silicon interposer covering the entire package, silicon bridges are embedded only where high-density die-to-die connections are required.
The enhanced EMIB-T implementation reportedly adds Through-Silicon Vias (TSVs) to these embedded bridges, enabling vertical power-delivery paths. It also incorporates Metal-Insulator-Metal (MIM) capacitors and dedicated ground structures.
These features are particularly relevant to high-power AI accelerators because rapid workload transitions can produce substantial transient current demands. A lower-impedance power-delivery network can help reduce voltage droop and improve power integrity under these conditions.
⚡ Why Google Could Consider EMIB-T #
Google has not publicly confirmed the reasons behind the reported packaging change. Nevertheless, several technical and commercial factors could make EMIB-T attractive for a next-generation TPU.
1. Improved power delivery #
Modern AI accelerators can operate at extremely high power levels and experience rapid changes in current demand.
EMIB-T’s TSV-enabled power paths, embedded MIM capacitors, and dedicated ground structures are designed to improve package-level power delivery. Reducing PDN impedance can improve transient response and help maintain stable voltage at high-performance compute dies.
For a TPU architecture with aggressive power and frequency targets, these characteristics could be particularly valuable.
2. Reduced large-area interposer dependency #
Large silicon interposers introduce their own thermomechanical challenges as package dimensions increase.
EMIB-T’s localized bridge architecture avoids placing silicon beneath the entire package. The organic substrate can handle lower-density routing while silicon bridges are reserved for regions where very high interconnect density is required.
This approach can potentially reduce some of the mechanical and manufacturing constraints associated with large-area interposers.
However, localized bridges do not eliminate thermomechanical engineering challenges. Instead, stress becomes concentrated around the embedded bridge structures, requiring careful package design and material optimization.
3. Packaging capacity diversification #
Supply availability is another possible factor.
AI accelerator demand has placed significant pressure on advanced packaging capacity, particularly for TSMC’s CoWoS ecosystem. Diversifying packaging suppliers could provide hyperscalers with additional manufacturing flexibility and reduce dependence on a single advanced-packaging platform.
Google already maintains a significant enterprise relationship with Intel through its server infrastructure, making Intel’s foundry and packaging capabilities a strategically relevant alternative.
🏭 Implications for Intel Foundry #
If the reported adoption is confirmed, the Humufish TPU could represent an important commercial validation of Intel’s advanced packaging strategy.
The significance would extend beyond a single TPU generation. Landing a hyperscale AI customer for advanced packaging would demonstrate that Intel’s packaging technologies can compete for workloads traditionally associated with TSMC’s ecosystem.
A stronger competitive position #
The advanced packaging market is increasingly becoming a strategic battleground between major semiconductor manufacturers.
AI accelerators require increasingly sophisticated combinations of:
- Compute chiplets
- High-bandwidth memory
- Silicon bridges
- Interposers
- High-density power delivery
- Advanced substrates
- Thermal-management structures
As these requirements become more demanding, packaging capability can influence foundry selection almost as much as transistor technology.
A high-profile Google TPU deployment would therefore provide Intel with an important reference design for its advanced packaging business.
📊 EMIB-T Is Not Automatically Better Than CoWoS-L #
The reported move should not be interpreted as evidence that EMIB-T is universally superior to CoWoS-L.
The two architectures make different engineering trade-offs. CoWoS-L provides extensive high-density routing across a large interposer structure, while EMIB-T concentrates advanced silicon interconnect technology in specific regions.
The optimal solution depends on the characteristics of the target accelerator, including:
- Die dimensions and placement
- Die-to-die bandwidth requirements
- HBM topology
- Power density
- Package dimensions
- Thermal constraints
- Signal-integrity requirements
- Manufacturing yield
- Cost targets
- Expected production volume
For some AI accelerator designs, the broad routing capabilities of an interposer may be preferable. For others, localized silicon bridges combined with advanced power delivery could provide a more attractive balance between performance, scalability, and manufacturing complexity.
🚀 What the Humufish Report Could Signal #
If Google’s 9th-generation Humufish TPU does adopt Intel’s EMIB-T, the decision would represent an important inflection point in the AI semiconductor packaging market.
Google’s historical reliance on TSMC CoWoS demonstrates how deeply established that platform has become in hyperscale AI infrastructure. A move to Intel’s packaging ecosystem would indicate that alternative architectures have become sufficiently mature to compete for demanding production workloads.
More importantly, the development highlights a broader industry trend: advanced packaging is becoming a core architectural technology rather than merely a manufacturing technology.
As AI accelerators continue moving toward larger dies, multi-die architectures, higher HBM bandwidth, and increasingly aggressive power envelopes, packaging decisions will play a growing role in determining system-level performance and scalability.
For Intel, a successful Humufish deployment could provide valuable evidence that EMIB-T is capable of challenging established CoWoS-based solutions. For Google, the reported transition could provide another route toward optimizing TPU performance, power integrity, package scalability, and supply-chain resilience.