Samsung and SK hynix Delay Hybrid Bonding for HBM4 as Memory Roadmaps Shift
Hybrid bonding, long expected to become one of the defining technologies of the HBM4 generation, is reportedly being pushed further down the roadmap by both Samsung and SK hynix. Instead of debuting with HBM4, the advanced packaging technology is now expected to arrive with later generations such as HBM4E or HBM5E.
The reported shift reflects changing industry priorities. Relaxed JEDEC package thickness specifications and slower-than-expected demand for higher-stack HBM products have reduced the immediate need for hybrid bonding, allowing memory manufacturers to prioritize production maturity while postponing a more complex manufacturing transition.
Why Hybrid Bonding Matters #
Hybrid bonding has been widely viewed as the next major evolution in high-bandwidth memory packaging. Unlike conventional thermocompression (TC) bonding, which relies on microbumps and underfill material to connect stacked DRAM dies, hybrid bonding creates direct copper-to-copper and dielectric-to-dielectric connections between memory layers.
This approach offers several advantages:
- Eliminates the insulating underfill layer between stacked dies.
- Improves thermal conductivity for dense memory stacks.
- Enables tighter vertical integration with reduced package height.
- Supports higher signal density and improved electrical performance.
These benefits become increasingly valuable as HBM continues moving toward higher layer counts and greater bandwidth for AI accelerators.
HBM4 No Longer Expected to Introduce Hybrid Bonding #
Earlier industry reports suggested that SK hynix had successfully validated 12-layer HBM devices using hybrid bonding and was preparing to introduce the technology during the HBM4 generation.
However, recent reports indicate both Samsung and SK hynix are reconsidering that timeline.
Instead of incorporating hybrid bonding into HBM4 production, manufacturers are reportedly planning to continue using refined thermocompression bonding while pursuing other thermal optimization techniques.
This allows companies to reduce manufacturing risk while preserving production capacity for rapidly growing AI memory demand.
JEDEC’s Revised Standards Reduce Immediate Pressure #
One of the largest factors behind the roadmap adjustment is a proposed revision to HBM package thickness specifications.
Earlier targets required increasingly thin memory stacks, making hybrid bonding highly attractive because it eliminated additional material between DRAM layers.
Under the revised proposal:
| Memory Generation | Previous Thickness Target | Revised Target |
|---|---|---|
| HBM4 | 775 μm | 825–900 μm |
| HBM5 | 900 μm | Approximately 1,000 μm |
The more relaxed mechanical requirements give manufacturers additional flexibility when designing future HBM products.
Without aggressive thickness constraints, existing thermocompression packaging techniques remain capable of meeting current specifications, reducing the urgency to transition to hybrid bonding.
Customer Demand Has Also Shifted #
Market demand has evolved alongside the technical standards.
Large AI accelerator customers have reportedly delayed their push toward higher-stack HBM configurations. As a result, industry discussions surrounding 16-layer HBM have slowed considerably.
Current expectations suggest:
- HBM4 will primarily focus on 12-layer products.
- HBM4E is also expected to remain largely centered around 12-layer stacks.
- Larger stack configurations may arrive later than originally anticipated.
With fewer immediate requirements for extreme stacking density, manufacturers have additional time to mature hybrid bonding before introducing it into volume production.
Updated Technology Roadmap #
Current industry expectations suggest the following progression:
| Product Generation | Bonding Technology |
|---|---|
| HBM4 | Refined thermocompression bonding |
| HBM4E | Potential introduction of hybrid bonding |
| HBM5E | Broad commercial deployment expected |
Rather than relying on hybrid bonding immediately, Samsung and SK hynix are reportedly focusing on improving heat dissipation through alternative package-level thermal designs while maintaining established manufacturing processes.
This strategy helps minimize production risk during a period of exceptionally strong demand for AI memory.
Why HBM5E May Be the Real Inflection Point #
Although hybrid bonding may not arrive with HBM4, industry expectations still position it as an essential technology for future HBM generations.
As memory stacks continue growing in complexity, several trends will increase the need for direct wafer-to-wafer or die-to-die bonding:
- Higher I/O density
- Greater bandwidth requirements
- Increased power density
- More demanding thermal constraints
- Larger DRAM stack heights
By the HBM5E generation, these scaling pressures are expected to make hybrid bonding far more difficult to avoid.
At that stage, the technology is likely to transition from a competitive advantage to a practical manufacturing requirement.
Industry Outlook #
The reported roadmap adjustment highlights a broader trend across the semiconductor industry: technical capability alone does not determine deployment schedules.
Although hybrid bonding offers meaningful improvements in thermal performance, package density, and electrical efficiency, manufacturers must balance those benefits against production maturity, customer demand, and evolving industry standards.
With JEDEC relaxing package thickness requirements and hyperscale customers delaying higher-stack memory adoption, Samsung and SK hynix appear to be prioritizing manufacturing stability over aggressive technology introduction.
Rather than signaling the end of hybrid bonding, the delay suggests memory vendors are waiting for the point where its advantages become economically and technically indispensable. Current industry expectations indicate that moment is more likely to arrive with HBM4E—and especially HBM5E—than with the first generation of HBM4 products.