TSMC vs Intel vs Samsung vs GF: The CPO Roadmap Race
Co-Packaged Optics (CPO) is moving from research demonstrations toward commercial AI infrastructure. On August 3, 2026, NVIDIA began shipping its Spectrum-X CPO switches to selected partners, while Broadcom continued small-batch deliveries of its 51.2T Bailly CPO switches.
These deployments mark an important transition for the industry. CPO is no longer simply a future packaging concept; it is becoming a practical technology for addressing the bandwidth density, power consumption, and signal-integrity challenges created by increasingly large AI clusters.
The competitive landscape extends well beyond switch vendors. TSMC, Intel, Samsung, and GlobalFoundries are pursuing fundamentally different strategies across silicon photonics, advanced packaging, optical compute interconnects, memory integration, and foundry services.
TSMC is leveraging its CoWoS and SoIC-X ecosystem, Intel is targeting optical I/O for compute silicon, Samsung is pursuing a vertically integrated logic-memory-packaging-optics platform, and GlobalFoundries is positioning itself as an open silicon-photonics foundry.
The technologies overlap, but their commercial targets and engineering trade-offs are substantially different.
🌐 TSMC: COUPE Extends the CoWoS Ecosystem #
TSMC’s silicon-photonics platform, COUPE (Compact Universal Photonic Engine), centers on integrating electrical and photonic dies using SoIC-X bump-less hybrid bonding.
The architecture stacks the EIC (Electrical Integrated Circuit) and PIC (Photonic Integrated Circuit) face-to-face. Electrical connections use sub-10μm-pitch Cu-Cu bonding, reducing the parasitic capacitance associated with conventional bump-based connections.
TSMC’s roadmap progressively moves COUPE from an optical-engine replacement technology toward deeply integrated optical interconnects.
COUPE Generation 1 #
The first-generation COUPE platform targets 1.6 Tbps of optical bandwidth in an OSFP-oriented package and entered mass production in 2026.
The primary objective is to validate the yield and reliability of SoIC-X integration for silicon-photonics applications, particularly as a replacement for conventional optical engines in 800G and 1.6T pluggable optical modules.
NVIDIA and Broadcom are among the early customers associated with the platform.
COUPE Generation 2 #
The second generation, planned for 2027, targets 6.4 Tbps and integrates COUPE directly with CoWoS packaging.
This represents a major architectural change. Rather than functioning as an independent optical engine, the photonic components become part of the same advanced package as the switch ASIC.
Broadcom’s Tomahawk 6 Davisson, a 102.4T-class switch, uses this approach with 16 optical engines connected to the switch ASIC through the CoWoS interposer.
COUPE Generation 3 #
TSMC’s longer-term direction targets approximately 12.8 Tbps, with the optical engine potentially moving inside the processor package itself.
The objective is true on-package optical connectivity for CPUs, GPUs, and other compute devices.
TSMC has not established a definitive mass-production schedule for this generation, but its expanding CoWoS capabilities—including the 9.5-reticle CoWoS roadmap and SoW-X system-on-wafer technology—provide potential packaging infrastructure for increasingly integrated optical architectures.
NVIDIA and Broadcom Validate the Architecture #
At Computex 2026, NVIDIA demonstrated two COUPE-based product families:
- Spectrum-X Photonics for Ethernet
- Quantum-X Photonics for InfiniBand
The highest-end Spectrum-X configuration reaches approximately 400 Tbps aggregate throughput across 512 800G ports, while NVIDIA claims substantially lower power consumption than conventional optical architectures.
Quantum-X targets InfiniBand with 115.2 Tbps across 144 800G ports.
Broadcom’s Tomahawk 6 Davisson reaches 102.4 Tbps, uses field-replaceable laser modules in an ELSFP form factor, and is specified at approximately 3.5W per 800G port.
The ELS Trade-Off #
TSMC’s COUPE architecture also inherits one of CPO’s major engineering challenges: the External Light Source (ELS).
Keeping the laser outside the package reduces exposure to the high temperatures generated by compute silicon and can simplify laser maintenance. However, it introduces demanding optical coupling requirements.
Fiber and optical-engine alignment must be extremely precise, while failure of the external light source still creates a serviceability challenge.
Broadcom’s field-replaceable ELSFP implementation on Davisson directly addresses this issue by allowing the laser module to be replaced without treating the entire CPO switch package as disposable.
🔬 Intel: OCI Targets Optical Compute Interconnects #
Intel’s Optical Compute Interconnect (OCI) takes a different path from TSMC.
The fundamental distinction is the target application. TSMC’s COUPE strategy is currently centered on switch CPO, replacing front-panel optical modules in scale-out networking. Intel’s OCI is primarily designed for scale-up compute interconnects, where optical links replace increasingly difficult-to-scale electrical connections between processors.
In this model, optical I/O can connect CPUs, GPUs, XPUs, and other accelerators within the same compute domain.
Intel’s 4 Tbps OCI Demonstration #
Intel demonstrated an OCI chiplet integrated with an Intel CPU in 2024, transmitting data through a bidirectional optical interface.
The prototype supports up to 4 Tbps bidirectional bandwidth, using:
- 64 channels operating at 32 Gbps per direction
- Eight fiber pairs
- Eight wavelengths per fiber
- Transmission distances of up to approximately 100 meters
- Energy efficiency of approximately 5 pJ/bit
Intel compared this with an approximately 15 pJ/bit reference value for conventional pluggable optical modules under the same comparison conditions.
The architecture is designed to move optical I/O closer to the compute package rather than treating optics as a separate networking subsystem.
Integrated Lasers vs External Light Sources #
One of Intel’s most important architectural differences is its focus on integrated lasers.
Intel’s OCI integrates the photonic and electronic components and incorporates on-chip lasers and semiconductor optical amplifiers.
An integrated light source can reduce optical path length, component count, and system complexity. The trade-off is thermal and reliability management because the laser is positioned much closer to high-power compute silicon.
External lasers have the opposite characteristics: they provide greater physical separation from the hottest components and can improve serviceability, but require external optical coupling and additional infrastructure.
Neither model is universally superior. The eventual choice will depend on thermal constraints, reliability, optical efficiency, cost, and field service requirements.
Intel’s Manufacturing Experience #
Intel’s silicon-photonics technology is not limited to laboratory demonstrations.
At the time of its OCI announcement, Intel reported shipping more than 8 million photonic integrated circuits containing over 32 million integrated lasers. These products had already been deployed in 100G, 200G, and 400G optical modules.
This manufacturing history gives Intel a substantial foundation for scaling photonic components into future compute-interconnect products.
OCI and the UCIe Ecosystem #
Intel’s primary uncertainty is therefore less about basic photonic capability and more about ecosystem adoption.
OCI uses UCIe rather than Ethernet as its external interface, positioning it naturally alongside processors and accelerators that support open chiplet interconnect architectures.
This makes Intel’s strategy a long-term bet on the expansion of the open chiplet ecosystem, while TSMC’s approach is more directly connected to its existing switch, foundry, and advanced-packaging customer base.
The two approaches may not compete directly in the short term, but their trajectories increasingly converge around on-package optical connectivity.
🏭 Samsung: Full-Stack CPO from Logic to Optical HBM #
Samsung has a fundamentally different advantage: it controls logic manufacturing, HBM, advanced packaging, and optical technologies within a single corporate structure.
During its 2024 Samsung Foundry Forum, the company presented its broader Samsung AI Solutions strategy, combining Foundry, Memory, and Advanced Packaging operations.
Samsung’s stated objective is to deliver integrated AI systems incorporating CPO, with an initial target around 2027 and a longer-term roadmap extending toward optical memory integration.
Samsung’s Five-Generation CPO Roadmap #
Samsung’s disclosed roadmap spans 2026 through 2030 and beyond:
| Generation | Target Year | Architecture | Primary Objective |
|---|---|---|---|
| Gen 1 PO | 2026 | Photonics Engine | CMOS-compatible optical engine |
| Gen 2 CPO | 2027 | Integrated CPO switch | 3.2T optical engines with 51.2T/102.4T switches |
| Gen 3 | 2028 | NPU/GPU + CPO | Optical interconnects inside compute packages |
| Gen 4 | 2029 | Optical Switch Fabric | Rack-to-rack all-optical connectivity |
| Gen 5 | 2030+ | Optical HBM + CPO | Optical links between HBM and compute |
Gen 1 Photonics Engine #
Samsung’s first-generation photonics engine uses a 300mm CMOS-compatible process and hybrid copper bonding between the EIC and PIC.
The objective is to create a relatively low-cost, high-efficiency optical engine with high-density electrical connections.
At OFC 2026, Samsung demonstrated a silicon-photonics chip fabricated on a 300mm wafer-compatible process. Its PDK included more than 40 component models covering modulators, photodetectors, SiN waveguides, and related photonic components.
Independent validation from imec reported a modulator data rate of 224 Gbps per lane.
Gen 2 to Gen 5 #
Samsung’s second generation is expected to integrate 3.2T optical engines with 51.2T and 102.4T switch ASICs using 2.5D packaging.
The third generation extends optical connectivity into Samsung-manufactured NPU and GPU packages.
By 2029, Samsung envisions an optical switch fabric capable of supporting rack-to-rack optical connectivity. Its most ambitious stage arrives in 2030 and beyond, with Optical HBM.
The Optical HBM concept seeks to replace portions of the conventional electrical interface between HBM and compute accelerators with optical links, potentially addressing future pin-count, bandwidth-density, and power challenges.
Samsung’s Vertical-Integration Advantage #
Samsung’s strongest differentiator is its ability to combine:
- Logic process technology
- HBM memory
- 2.5D/3D packaging
- Silicon photonics
- Optical interconnects
Its hybrid copper bonding technology also benefits from experience in advanced HBM stacking. Samsung has indicated that the same technology can be repurposed for dense EIC-PIC connections, with pitches around 10μm.
This creates the possibility of a turnkey AI platform where customers do not need to coordinate separate logic, memory, packaging, and optical suppliers.
The downside is equally significant: vertical integration concentrates risk. A yield, performance, or supply problem in any individual component can affect the entire system-level solution.
Samsung therefore needs to demonstrate not only technological completeness but also stable yield, predictable delivery, and competitive system economics.
🏗️ GlobalFoundries: The Open Silicon-Photonics Foundry #
GlobalFoundries approaches CPO from a different starting point.
Unlike TSMC, Intel, and Samsung, GlobalFoundries is not primarily trying to build a complete AI compute platform. Its strategic position is as a specialized, open silicon-photonics manufacturing partner.
Optical modulators, photodetectors, RF circuits, and related components have substantially different manufacturing requirements from leading-edge CPU and GPU logic.
For photonics, optical loss, analog characteristics, material properties, process stability, and manufacturing cost can be more important than transistor density.
GF Fotonix #
GlobalFoundries introduced GF Fotonix in 2022, combining 300mm silicon-photonics capabilities with RF-CMOS on a common wafer platform.
The platform was subsequently upgraded to support higher per-wavelength data rates, greater design flexibility, and turnkey packaging capabilities.
This positions GlobalFoundries as a manufacturing layer that can serve fabless optical-device designers without requiring them to operate their own photonics fabs.
SCALE CPO Platform #
In May 2026, GlobalFoundries introduced its SCALE optical module platform for CPO applications.
SCALE supports both CWDM and DWDM architectures and has demonstrated bidirectional 8-wavelength and 16-wavelength DWDM configurations.
The platform incorporates:
- 50Gbps and 100Gbps microring modulators
- Integrated photodetectors
- TSV and Cu-pad structures
- 2.5D/3D stacking support
- Detachable fiber optics
- Known Good Die testing
These features emphasize manufacturability and serviceability rather than simply maximizing headline bandwidth.
GlobalFoundries has also positioned SCALE around OCI MSA specifications, targeting modern AI scale-out architectures.
Serviceability as a Competitive Feature #
The emphasis on detachable optical connections and KGD testing is particularly important.
CPO systems combine expensive electronic and photonic components into tightly integrated packages. If a single component fails after assembly, replacing the entire package can be economically and operationally difficult.
By enabling optical components and dies to be tested and managed independently where possible, GlobalFoundries is addressing one of the major barriers to large-scale CPO deployment.
Its strategy is therefore less about owning the entire AI stack and more about becoming an indispensable open manufacturing layer for photonic components and optical engines.
⚔️ Four Foundries, Four CPO Strategies #
The strategic differences become clearer when the four companies are compared directly:
| Dimension | TSMC | Intel | Samsung | GlobalFoundries |
|---|---|---|---|---|
| Core Strategy | Advanced packaging + silicon photonics | Optical compute interconnect | Full-stack AI integration | Open silicon-photonics foundry |
| Key Platform | COUPE + SoIC-X | OCI chiplet | PO + HCB | GF Fotonix + SCALE |
| Primary Target | CPO switches, then compute | Scale-up compute interconnect | Switches, compute, optical HBM | Optical engines and CPO components |
| Light Source | Primarily external | Integrated/on-chip | External and integrated | Multiple coupling approaches |
| Business Model | Foundry + advanced packaging | Chiplet ecosystem | IDM turnkey solution | Pure-play foundry |
| Key Advantage | CoWoS ecosystem | Photonic integration | Vertical integration | Open manufacturing |
| Primary Risk | ELS and serviceability | Ecosystem adoption | System-level execution | Dependence on external system designers |
The distinction is important because these companies are not necessarily competing for exactly the same CPO market today.
TSMC has the strongest immediate connection to high-volume AI networking through its advanced-packaging ecosystem. Intel is positioning optics as an extension of the compute package itself. Samsung is attempting to own the complete AI hardware stack, while GlobalFoundries is targeting the photonics manufacturing layer underneath the system.
🔥 Why CPO Still Has Major Engineering Challenges #
CPO addresses fundamental scaling problems in AI networking, but commercialization requires solving several difficult engineering issues.
Thermal Management #
High-performance compute dies generate substantial heat, while optical devices can be sensitive to temperature variation.
Placing photonic components close to GPUs, CPUs, or switch ASICs therefore requires sophisticated thermal management and optical compensation mechanisms.
The closer optics move to high-power compute, the more important this trade-off becomes.
Testing and Yield #
A CPO package can contain:
- Compute or switch ASICs
- Electrical interface dies
- Photonic integrated circuits
- Optical engines
- Fiber interfaces
- Advanced interconnect structures
A single failed component can potentially compromise an otherwise functional and expensive package.
Known Good Die (KGD) testing is therefore critical. Photonic and electronic components need to be screened before final assembly wherever possible to reduce package-level yield losses.
Serviceability #
Traditional pluggable optics have a major operational advantage: a failed optical module can be removed from the front panel and replaced quickly.
CPO changes that model by embedding optical components much closer to the switch or compute package.
This creates a difficult question for data-center operators: how should an optical component be serviced when it is physically integrated with the compute system?
Field-replaceable laser modules, detachable fibers, and modular optical architectures are emerging as potential answers.
Standards and Ecosystem Compatibility #
CPO also requires greater standardization across optical interfaces, chiplet protocols, packaging structures, laser architectures, and testing methodologies.
Standards initiatives such as OCI MSA and open chiplet interfaces are helping establish common ground, but vendor-specific implementations remain prevalent.
For CPO to move from a small number of proprietary deployments to a broad infrastructure technology, interoperability will become increasingly important.
🔮 CPO Will Complement Rather Than Immediately Replace Pluggable Optics #
CPO is unlikely to eliminate copper links and conventional pluggable optical modules overnight.
Different workloads require different combinations of distance, bandwidth, latency, power efficiency, serviceability, and cost. Pluggable optics will remain attractive where flexibility and field replacement matter, while copper remains effective for shorter and lower-cost connections.
CPO becomes increasingly compelling as AI clusters scale and the power and signal-integrity costs of electrical interconnects become harder to manage.
The more important shift is strategic: the AI hardware race is expanding beyond faster CPUs, GPUs, and accelerators toward more efficient communication between them.
As AI systems increasingly depend on the interaction between compute, HBM, advanced packaging, electrical I/O, and optical networking, foundries are evolving from pure wafer manufacturers into system-enabling technology providers.
The eventual winners in CPO will not necessarily be the companies with the highest headline bandwidth. They will be the companies capable of delivering optical interconnects that are manufacturable at scale, thermally manageable, testable, reliable, serviceable, and economically viable.
That makes CPO one of the most important battlegrounds in the next generation of AI infrastructure.