TSMC and Intel Accelerate Advanced Packaging as Market Tops $8.1 Billion
The semiconductor industry is entering a new packaging era. As AI accelerators and high-performance computing (HPC) processors continue to grow in size, complexity, and power density, traditional packaging technologies are approaching their practical limits. In response, industry leaders such as TSMC and Intel are rapidly investing in glass substrates and Fan-Out Panel-Level Packaging (FOPLP), two technologies widely viewed as foundational for next-generation chiplet-based systems.
According to Counterpoint Research’s 2026 industry outlook, the combined FOPLP and glass substrate packaging market is projected to expand from approximately $650 million in 2024 to more than $8.1 billion by 2030. This growth reflects the increasing demand for higher interconnect density, improved thermal performance, and lower packaging costs across AI and HPC deployments.
ð Advanced Packaging Market Enters a High-Growth Phase #
The rapid rise of generative AI, large-scale training clusters, and advanced HPC workloads is fundamentally reshaping semiconductor packaging requirements.
Traditional package architectures were designed around monolithic chips and moderate bandwidth requirements. Modern AI processors, however, increasingly rely on:
- Multi-die chiplet architectures
- High-bandwidth memory (HBM)
- Massive interconnect densities
- Larger package footprints
- Improved power delivery networks
These requirements are accelerating investment in advanced packaging technologies capable of supporting increasingly complex silicon systems.
Market Growth Outlook #
Counterpoint Research projects exceptional growth for the sector:
| Year | Market Size |
|---|---|
| 2024 | $650 Million |
| 2030 | $8.1+ Billion |
This represents one of the fastest-growing segments within the semiconductor industry, driven primarily by AI infrastructure investments and HPC deployments.
Revenue Composition by 2030 #
Panel-level packaging is expected to become the primary growth engine of the market.
Key projections include:
- FOPLP accounting for approximately 45.6% of total market revenue.
- Continued expansion of advanced packaging capacity across East Asia.
- Increased investment in domestic packaging ecosystems in the United States.
Manufacturing Capacity Distribution #
East Asia is expected to remain the global center of advanced packaging production.
By 2030:
- Taiwan
- Japan
- Mainland China
are projected to collectively account for approximately 84.8% of global panel-level packaging capacity.
Meanwhile, Intel’s advanced packaging facilities in New Mexico are expected to serve as a critical domestic manufacturing hub for the United States.
ð Why Glass Substrates and FOPLP Matter #
Glass substrates and panel-level packaging are often discussed together because their benefits are highly complementary.
Compared with conventional organic substrate packaging, the combined approach offers substantial advantages for large AI and HPC processors.
Larger Packaging Area #
Traditional semiconductor manufacturing relies on circular wafers.
Panel-level packaging replaces these with large rectangular panels, enabling:
- More efficient space utilization
- Higher die counts per panel
- Improved economics for large packages
- Better accommodation of HBM stacks and chiplets
This becomes increasingly important as AI processors continue growing in physical size.
Higher Interconnect Density #
Glass substrates provide significantly finer routing capabilities than conventional organic materials.
Benefits include:
- Increased signal density
- Improved signal integrity
- Better support for high-speed interfaces
- Enhanced scalability for chiplet architectures
As package complexity rises, these advantages become increasingly valuable.
Improved Dimensional Stability #
Glass exhibits superior mechanical characteristics compared with organic substrates.
Notable advantages include:
- Reduced warpage
- Better thermal stability
- Improved manufacturing precision
- Greater suitability for ultra-large packages
These properties are particularly important for advanced AI processors that integrate multiple compute dies and memory stacks within a single package.
ð TSMC’s CoPoS Strategy #
TSMC is actively advancing its Chip-on-Panel-on-Substrate (CoPoS) roadmap as part of its next-generation packaging strategy.
The company’s initial deployment plans focus on organic substrates before eventually transitioning toward glass-core substrate implementations.
Expected Benefits #
Industry estimates suggest that glass-core adoption could deliver substantial manufacturing improvements:
- Packaging cost reductions approaching 30%
- Material utilization rates exceeding 90%
- Significant reductions in geometric waste
For comparison, conventional wafer-based approaches often achieve material utilization rates below 70%.
As AI package sizes continue expanding, these efficiency gains become increasingly important for controlling manufacturing costs.
Broader Industry Participation #
TSMC is not alone in pursuing this transition.
Major industry participants investing in related technologies include:
- Samsung Electro-Mechanics
- ASE Technology
- PTI
- Numerous substrate and equipment suppliers
The ecosystem-wide investment signals growing confidence that glass substrates will become a mainstream packaging technology during the coming decade.
ðŽ Intel’s Early Commitment to Glass Substrates #
Intel was among the first major semiconductor companies to publicly outline a glass substrate roadmap.
The company introduced its vision for glass-core packaging technologies as early as 2023, positioning itself as a key driver of next-generation packaging innovation.
Commercialization Timeline #
Intel and its supply chain partners are targeting commercial deployment of glass-core substrates within the next several years.
Successful execution could provide several strategic benefits:
- Strengthening domestic packaging capabilities
- Supporting advanced chiplet architectures
- Enhancing competitiveness in AI and HPC markets
- Expanding packaging capacity outside East Asia
The success of this initiative will play a significant role in shaping the future of the U.S. advanced packaging ecosystem.
Why Industry Interest Continues to Grow #
As package complexity increases, traditional organic substrates face mounting technical challenges.
Glass substrates address several critical issues simultaneously:
- Higher interconnect density
- Better dimensional control
- Reduced warpage
- Improved support for large chiplet-based systems
These advantages explain why nearly every major semiconductor manufacturer is evaluating glass-based solutions.
âïļ Technical Challenges Still Blocking Mass Adoption #
Despite the strong market momentum, several major engineering obstacles remain before glass substrates and panel-level packaging can achieve widespread high-volume manufacturing.
Lack of Panel Size Standardization #
One of the industry’s most pressing issues is the absence of a unified panel format.
Current proposals include dimensions such as:
- 310 Ã 310 mm
- 515 Ã 510 mm
- 620 Ã 750 mm
Without standardization, equipment vendors face difficulties designing scalable manufacturing platforms.
This fragmentation slows ecosystem development and increases implementation costs.
Through-Glass Via (TGV) Manufacturing #
Through-Glass Vias (TGVs) are essential for enabling electrical connections through glass substrates.
However, manufacturing consistent sub-10 Ξm vias remains extremely challenging.
Key obstacles include:
- Laser drilling variability
- Micro-crack formation
- Yield degradation
- Process repeatability
Achieving production-scale reliability remains a major focus area for equipment and materials suppliers.
Metallization and Surface Flatness #
Large glass panels introduce additional manufacturing complexities.
Challenges include:
- Uniform copper deposition
- Reliable deep-via metallization
- Nanometer-scale flatness control
- Long-term mechanical stability
These issues directly impact yield, performance, and manufacturing cost.
As a result, they remain among the most critical barriers to large-scale commercialization.
ðŪ What Comes Next for Advanced Packaging #
The trajectory of advanced packaging is increasingly tied to the future of AI infrastructure.
As chipmakers continue pushing beyond traditional monolithic designs, advanced packaging is becoming a primary driver of system-level performance improvements.
Key trends expected over the next several years include:
- Wider adoption of chiplet architectures
- Increasing integration of HBM memory
- Growth of panel-level packaging capacity
- Commercial deployment of glass-core substrates
- Expanded investment from foundries, OSATs, and substrate suppliers
The pace of adoption will ultimately depend on how quickly the industry resolves standardization and manufacturing challenges.
ð Conclusion #
Glass substrates and panel-level packaging are emerging as critical technologies for the next generation of AI and HPC systems. Driven by growing package complexity and soaring demand for high-performance computing, industry leaders such as TSMC and Intel are accelerating investments in these advanced packaging architectures.
With the market expected to expand from $650 million in 2024 to more than $8.1 billion by 2030, advanced packaging is rapidly becoming one of the most strategically important segments of the semiconductor industry. However, widespread adoption still depends on solving key technical challenges, including panel standardization, Through-Glass Via manufacturing, and large-scale process stability.
For semiconductor vendors, investors, and infrastructure providers alike, progress in these areas will serve as one of the clearest indicators of how quickly next-generation AI hardware can scale in the years ahead.