Intel’s AI Memory Comeback: ZAM, XBM and 512GB Stacks
Intel could be preparing a return to the memory market, nearly four decades after exiting the commodity DRAM business.
Intel CEO Lip-Bu Tan has recently emphasized the strategic importance of memory in the AI era and indicated that Intel is considering a renewed role in memory technology. This time, however, the company is not expected to return to commodity DRAM. Instead, Intel is reportedly targeting specialized high-bandwidth and high-density memory technologies for AI and data-center workloads.
Among the technologies associated with Intel’s new memory strategy are XBM and ZAM, with ZAM reportedly targeting stacked memory capacities of up to 512GB per chip stack.
At the same time, Intel engineers continue to work on Linux memory management, including an optimization that dramatically reduces the time required for memory hotplug operations in virtual machines and CXL-based systems.
🕰️ Intel’s Long and Complicated Memory History #
Intel’s connection to memory predates its identity as an x86 processor company.
Founded in 1968, Intel initially focused on memory products. In 1969, the company introduced the Intel 3101, an early commercial SRAM product, at a time when magnetic-core memory remained widely used.
In 1970, Intel introduced the 1103 DRAM, which became a major commercial success and established Intel as an important memory manufacturer.
From DRAM to CPUs #
The subsequent history is closely connected to Intel’s eventual transformation into a processor company.
During the 1970s and 1980s, Japanese semiconductor manufacturers placed intense pricing pressure on the U.S. memory industry. Intel struggled to compete in commodity memory and ultimately exited the DRAM business in 1985.
One of the better-known consequences was Intel’s increasing focus on microprocessors. The company had been involved in developing custom processors for Japanese customers, helping establish the foundation for the x86 business that eventually became central to Intel’s identity.
Intel later experimented with other memory technologies, including RDRAM through its relationship with Rambus during the late 1990s and early 2000s.
The company subsequently rebuilt a major NAND flash business and, together with Micron, developed 3D XPoint, which was commercialized under the Optane brand.
NAND and Optane Eventually Disappeared #
Intel’s NAND business eventually became part of SK hynix, while Optane was discontinued after Intel and Micron ended their 3D XPoint partnership and the technology struggled with manufacturing economics and market adoption.
That history is important because the current AI boom has created an environment in which memory capacity, bandwidth, latency, and power efficiency have become central constraints for data-center systems.
Intel’s latest memory ambitions are therefore aimed at a different market from the commodity DRAM business it abandoned decades ago.
🤖 Intel’s New AI Memory Strategy #
Intel’s emerging strategy reportedly centers on specialized memory technologies rather than conventional DRAM production.
Two technologies have attracted particular attention:
- XBM, a high-bandwidth memory architecture intended to compete in applications traditionally served by HBM.
- ZAM, a vertically stacked DRAM technology developed with SoftBank subsidiary SAIMEMORY.
Both approaches target the growing requirements of AI accelerators, where conventional memory architectures face increasing constraints in bandwidth, capacity, power consumption, and thermal management.
🧱 XBM Targets High-Bandwidth AI Memory #
XBM is described as a high-bandwidth memory architecture that uses a different physical arrangement from conventional HBM.
One of its notable concepts is placing transistors on the backside of the memory structure.
The objective is to reduce manufacturing complexity while improving power efficiency and potentially increasing the scalability of high-bandwidth memory.
The technology is positioned as an alternative approach to HBM rather than simply another generation of conventional stacked HBM.
Its practical competitiveness will ultimately depend on manufacturing yield, bandwidth, latency, energy efficiency, packaging requirements, and ecosystem support.
🧬 ZAM Targets Extremely High Memory Density #
ZAM, short for Z-Angle Memory, takes a different approach.
Intel is reportedly developing the technology together with SAIMEMORY, a SoftBank subsidiary, under a Japanese government-supported research and development program.
The basic concept is to vertically stack multiple DRAM layers using a specialized bonding and interconnect architecture.
A Different Approach to Memory Stacking #
Conventional HBM relies on vertically stacked memory dies connected through technologies such as through-silicon vias.
ZAM instead uses a proprietary Z-angle interconnect architecture intended to arrange and connect memory dies in a different geometric configuration.
The design is aimed at addressing two major challenges facing increasingly dense memory systems:
- Heat dissipation.
- Power consumption.
According to the claims associated with the technology, the angled stacking arrangement could improve thermal transfer compared with conventional approaches.
The architecture is also intended to simplify aspects of manufacturing and provide a path toward higher-density memory products.
Up to 512GB Per Stack #
One of the most striking claims surrounding ZAM is a potential capacity of up to 512GB in a single memory stack.
The technology has also been described as potentially consuming 40% to 50% less power than conventional HBM, although these figures remain technology claims rather than independently established production benchmarks.
If those targets can be achieved in commercial products, the combination of extremely high capacity and lower power consumption could make ZAM relevant to AI systems that increasingly require large amounts of memory close to accelerators.
Japanese media reports have suggested that risk production could begin as early as 2027, with commercial deployment potentially following around 2029.
These dates remain dependent on development progress, manufacturing readiness, yield, and customer adoption.
📈 AI Is Intensifying the Global Memory Crunch #
Intel’s renewed interest in specialized memory comes as the semiconductor industry faces rapidly increasing demand for DRAM and NAND.
Recent statements from industry executives illustrate the disagreement over how long current shortages will persist.
Acer Chairman Jason Chen has questioned forecasts that memory shortages and price increases will continue through the end of next year. He suggested that public statements about shortages could partly reflect the constraints imposed by antitrust rules on direct coordination between suppliers.
Phison Electronics CEO K.S. Pua, however, has publicly disputed that assessment and argued that the industry’s supply constraints could persist for several more years.
AI Data Centers Are Changing Memory Demand #
The underlying structural issue is straightforward: AI infrastructure requires enormous quantities of memory and storage.
Over the past several years, memory manufacturers have directed substantial capacity toward server products. At the same time, AI workloads are creating additional demand for:
- HBM.
- Server DRAM.
- Enterprise SSDs.
- High-capacity NAND.
- CXL-attached memory.
- Accelerator-local memory.
This creates competition for manufacturing capacity even as conventional cloud and enterprise workloads continue expanding.
Large-scale data-center construction further compounds the problem because each new AI cluster requires not only accelerators but also substantial amounts of host memory, storage, networking, and power infrastructure.
Relief May Take Years #
Several industry forecasts suggest that meaningful relief may not arrive until 2028 or later, when new manufacturing capacity begins entering production.
Even additional fabs may not completely eliminate the structural supply-demand imbalance.
One previous projection cited in the supplied material estimated that by 2030, total memory manufacturing capacity—including planned fabs and expansions—could satisfy only about 76% of projected demand.
Such forecasts remain subject to substantial uncertainty, particularly because AI infrastructure investment, memory pricing, manufacturing yields, and technology transitions can all change rapidly.
💾 Linux Kernel Optimization Makes Memory Hotplug Faster #
The memory story is not limited to manufacturing.
Intel engineers are also contributing to software infrastructure designed to make large-scale memory systems easier to manage.
An optimization led by Intel engineer Yuan Liu has been merged into the Linux kernel’s for-next branch for the memory-management subsystem. The work targets the performance of memory hotplug domain continuity checking.
Memory hotplug allows system memory to be dynamically added or removed while a system is running.
This capability is increasingly relevant to virtual machines and systems using Compute Express Link (CXL) to attach additional memory resources.
Avoiding Expensive Page-Block Scans #
The optimization reduces the need to perform full page-block scans across an entire memory domain when validating continuity.
Testing in virtual-machine environments reportedly showed substantial improvements:
- Memory hot-add time reduced by up to 81%.
- Memory hot-remove time reduced by up to 75%.
- A 512GB hot-add operation dropped from approximately 36 seconds to 7 seconds.
- A 512GB hot-remove operation dropped from approximately 36 seconds to 9 seconds.
These figures represent improvements of roughly 81% and 75%, respectively, in the tested configurations.
The optimization is expected to be submitted during the Linux 7.4 merge window.
🔗 CXL Makes Efficient Memory Hotplug More Important #
Samsung testing has also reportedly evaluated the optimization in CXL memory scenarios.
For CXL-based memory hotplug, the reported execution-time reductions were:
- 35% for a 256GB configuration.
- 52% for a 512GB configuration.
CXL allows systems to attach additional memory resources through a high-speed interconnect rather than treating all memory as permanently attached to the CPU’s conventional memory channels.
This opens the door to more flexible memory pooling and dynamic resource allocation.
Dynamic Memory for Cloud and CXL Systems #
Typical applications for memory hotplug include:
- Dynamically expanding virtual-machine memory.
- Removing memory from systems without shutting them down.
- Allocating CXL-attached memory dynamically.
- Rebalancing memory resources across data-center workloads.
- Building larger pooled-memory architectures.
As CXL adoption increases, the ability to add and remove large memory regions efficiently becomes increasingly important.
An operation that takes tens of seconds may become a significant bottleneck when memory resources are being orchestrated dynamically across large fleets of virtual machines.
🏭 Intel’s Memory Strategy Is Expanding Beyond Chips #
The combination of Intel’s hardware initiatives and Linux engineering work points toward a broader change in how the company approaches memory.
At the hardware level, ZAM and XBM target the physical limitations of AI memory, including capacity, bandwidth, thermal density, and power consumption.
At the software level, Linux memory-management improvements make it easier to dynamically deploy increasingly large memory resources.
The two trends are complementary.
A future AI server may need enormous amounts of memory that can be dynamically allocated between CPUs, accelerators, virtual machines, and CXL memory pools. Hardware density alone is not enough; the operating system and virtualization stack must also manage those resources efficiently.
🔮 Intel’s Memory Comeback Could Look Very Different This Time #
Intel’s historical memory business was built around commodity technologies such as SRAM and DRAM. Its second attempt is shaping up differently.
Rather than competing directly with established DRAM vendors on commodity memory volume, Intel is targeting specialized technologies for an AI-driven market where bandwidth, density, power efficiency, packaging, and memory pooling are becoming increasingly important.
ZAM’s reported 512GB-per-stack target is particularly ambitious, while XBM represents another attempt to rethink how high-bandwidth memory is manufactured and integrated.
Neither technology has yet established itself as a mass-market replacement for HBM, and claims regarding capacity, power efficiency, production timing, and manufacturing advantages still require validation through commercial products.
At the same time, the rapid growth of AI infrastructure is making memory one of the defining constraints of modern data-center design.
If Intel can successfully turn its new memory technologies into scalable products—and simultaneously improve the software infrastructure needed to manage massive memory pools—the company’s return to memory could be considerably different from its previous attempts.
This time, Intel is not simply trying to sell more memory chips. It is targeting the architecture of AI memory itself.