SK hynix and SanDisk Launch Open HBF Standard for AI Memory

SK hynix and SanDisk Launch Open HBF Standard for AI Memory

SK hynix and SanDisk have jointly released the industry’s first High Bandwidth Flash (HBF) technical specification, introducing a new storage and memory tier designed specifically for large-scale AI infrastructure.

Unveiled at FMS 2026 in Santa Clara, the specification defines an open framework for positioning NAND-based HBF between high-bandwidth memory such as HBM and conventional SSD storage.

The objective is straightforward: provide AI systems with significantly more capacity than HBM while delivering substantially higher bandwidth than traditional SSDs, helping address the growing gap between compute performance, memory capacity, and storage economics.

The specification was submitted through the Open Compute Project (OCP), making HBF an open industry framework rather than a proprietary interface.

The HBF consortium was established only six months before the specification release, while SK hynix and SanDisk began their standardization collaboration approximately one year earlier. Google and Tenstorrent have also joined the consortium, signaling broader industry interest in alternative memory hierarchies for AI infrastructure.

🧩 What Is High Bandwidth Flash?

#

HBF is designed to occupy an intermediate position in the AI memory hierarchy:

        Higher Bandwidth
              ▲
              │
             HBM
              │
              │
             HBF
              │
              │
            SSD
              │
              ▼
        Higher Capacity

HBM provides extremely high bandwidth but remains expensive and relatively limited in capacity.

SSDs provide much greater capacity at significantly lower cost per bit, but their bandwidth and latency are far less suitable for workloads that continuously exchange data with accelerators.

HBF attempts to bridge that gap by using NAND flash as the underlying storage technology while introducing a much higher-bandwidth interface and device architecture.

This creates a new tier that could be particularly useful for AI inference, where models can require enormous amounts of data while not every byte needs to reside in the most expensive HBM.

⚡ HBF Reaches Up to 3.0 TB/s of Bandwidth

#

The initial HBF specification supports capacities of up to 512GB using either 8-high or 16-high NAND die stacks.

It defines three bandwidth grades spanning approximately:

The top specification reaches approximately 3.0 TB/s, putting HBF far above the bandwidth typically associated with conventional SSD interfaces.

This is the central architectural proposition behind HBF: NAND does not need to compete directly with HBM on every metric. Instead, it can provide a larger and more economical capacity tier with enough bandwidth to serve workloads that would otherwise create pressure on HBM capacity.

Up to 512GB per HBF Device

#

The initial specification supports up to 512GB of capacity.

The technology uses vertically stacked NAND dies in either 8-high or 16-high configurations, allowing the physical package to provide substantially more capacity than conventional high-bandwidth memory devices.

This makes HBF particularly interesting for AI systems where memory capacity is becoming a limiting factor as model sizes and inference context windows continue to grow.

🔗 UCIe Connects HBF to CPUs and GPUs

#

One of the most important architectural choices is the adoption of Universal Chiplet Interconnect Express (UCIe).

Rather than defining another proprietary connection mechanism, HBF uses UCIe as an open chiplet interface that can connect HBF devices with heterogeneous processors.

Potential hosts include:

• GPUs
• CPUs
• AI accelerators
• Other chiplet-based compute devices

A simplified architecture looks like this:

              CPU
               │
               │
        ┌──────┴──────┐
        │     UCIe    │
        └──────┬──────┘
               │
        ┌──────┴──────┐
        │     HBF     │
        │ NAND Flash  │
        └─────────────┘
               ▲
               │
             GPU

UCIe gives HBF a path toward interoperability across heterogeneous compute platforms.

That is particularly significant for AI infrastructure because future servers are increasingly built from combinations of CPUs, GPUs, custom accelerators, networking chips, and other chiplets rather than a single monolithic processor architecture.

🧠 SK hynix Pushes a Tiered Memory Architecture

#

At FMS 2026, SK hynix executives Kim Chun-sung and Kang Uk-song described Tiered Memory as an increasingly important direction for AI infrastructure.

The basic idea is that future AI systems should not rely on a single memory technology.

Instead, different memory tiers can be optimized for different combinations of bandwidth, capacity, latency, and cost:

For increasingly agentic AI workloads, data may need to move between these tiers dynamically.

A system could keep the most performance-sensitive data in HBM, place larger working sets in HBF, and retain less frequently accessed information on SSDs.

This approach could reduce pressure on expensive HBM while avoiding the severe performance penalty of accessing all large-scale data directly from SSD storage.

🔥 HBF Targets the AI Memory Wall

#

The growing AI memory problem is often described as the memory wall.

Modern accelerators can process enormous quantities of data, but feeding those compute engines with enough data at the required bandwidth becomes increasingly difficult as models grow.

The problem has two dimensions:

Bandwidth: How quickly can data reach the accelerator?

Capacity: How much data can remain close enough to the accelerator to be useful?

HBM addresses the first problem exceptionally well, but its capacity and cost remain constraints.

SSDs address capacity and cost, but their performance characteristics make them unsuitable as a direct replacement for HBM.

HBF attempts to occupy the middle ground.

HBM
│
├── Highest bandwidth
├── Lowest practical latency
└── Limited capacity / high cost
          │
          ▼
        HBF
          │
├── Higher capacity
├── Much higher bandwidth than SSD
└── NAND economics
          │
          ▼
        SSD
│
├── Massive capacity
├── Low cost per bit
└── Much lower bandwidth

If HBF can deliver its proposed bandwidth levels at NAND economics, it could provide system architects with another tool for balancing AI performance and infrastructure cost.

🌐 Open Standardization Could Be HBF’s Biggest Advantage

#

The decision to submit the HBF specification through the Open Compute Project is strategically important.

A proprietary memory technology can offer strong integration but risks creating a closed ecosystem. An open standard can instead encourage multiple vendors to build compatible devices and controllers.

The involvement of Google and Tenstorrent further broadens the potential ecosystem beyond traditional NAND manufacturers.

Combined with UCIe, the approach could allow HBF to connect to heterogeneous compute platforms without requiring every processor vendor to create a proprietary interface.

For hyperscale AI infrastructure, that interoperability could become as important as raw bandwidth.

🏗️ SK hynix Also Demonstrates 375-Layer V10 4D NAND

#

HBF was not the only NAND technology SK hynix showcased at FMS 2026.

The company publicly demonstrated its 375-layer V10 4D NAND for the first time.

According to SK hynix, the new generation achieves up to a 2.5× improvement in power efficiency compared with the previous generation.

The company plans to begin mass production of enterprise SSDs based on the technology early next year.

The timing is significant because AI data centers increasingly face power constraints alongside capacity and performance requirements.

Higher NAND density can reduce the physical footprint required for storage, while better power efficiency can help control the growing energy cost of large-scale AI infrastructure.

🔬 HBF Could Change the AI Memory Hierarchy

#

The significance of HBF is not simply that NAND flash is becoming faster.

The larger change is architectural.

Instead of treating storage as a separate layer that sits far away from GPU memory, HBF proposes bringing a portion of NAND-based capacity much closer to compute through high-bandwidth interfaces and chiplet integration.

That creates a possible future architecture:

                 AI Accelerators
                       │
                       ▼
                  ┌─────────┐
                  │   HBM   │
                  └────┬────┘
                       │
                  ┌────▼────┐
                  │   HBF   │
                  └────┬────┘
                       │
                  ┌────▼────┐
                  │   SSD   │
                  └────┬────┘
                       │
                  ┌────▼────┐
                  │ Storage │
                  └─────────┘

Such a hierarchy could allow system architects to match different data types with the memory tier that offers the most appropriate combination of speed, capacity, and cost.

For inference workloads in particular, this could become increasingly valuable as models, context windows, retrieval databases, and agent state continue to expand.

📊 Why HBF Matters for AI Inference

#

AI inference has different memory requirements from traditional CPU workloads.

Large language models can require hundreds of gigabytes of memory simply to hold model weights, while KV caches, intermediate activations, retrieval data, and agent state can further increase the working set.

Keeping everything in HBM is expensive and often impractical.

Moving everything to SSD storage, meanwhile, can introduce severe bandwidth and latency limitations.

HBF provides a potential middle layer:

HBM for hot data → HBF for larger active datasets → SSD for persistent data

This tiered approach could allow AI servers to use expensive high-bandwidth memory more efficiently rather than attempting to store every piece of data in HBM.

🧭 What Comes Next for HBF?

#

The initial specification establishes an important foundation, but widespread adoption will depend on several factors.

Key questions include:

• How much real-world latency will HBF deliver?
• How efficiently can GPUs access HBF?
• What controller architecture will be required?
• How will HBF scale across multiple devices?
• Can UCIe provide sufficient bandwidth and interoperability in production systems?
• How will operating systems and AI runtimes manage HBM, HBF, and SSD tiers?
• What will the cost per usable GB look like at scale?
• How much power will high-bandwidth NAND devices consume?

The answers will determine whether HBF becomes a broadly deployed AI memory tier or remains a specialized architecture for certain workloads.

🏁 Conclusion

#

SK hynix and SanDisk’s HBF specification represents a significant attempt to redefine the boundary between memory and storage.

By combining NAND flash capacity, multi-TB/s-class bandwidth, UCIe connectivity, and open standardization through OCP, HBF is designed to occupy the gap between HBM and SSDs.

The concept is particularly compelling for AI infrastructure because neither HBM nor SSDs alone provides an ideal balance of bandwidth, capacity, and cost for increasingly large and agentic workloads.

If the ecosystem develops as planned, future AI servers could increasingly rely on a multi-tier architecture in which HBM handles the hottest data, HBF provides a larger high-bandwidth working tier, and SSDs supply persistent capacity.

The most important development is therefore not simply faster NAND. HBF represents an attempt to make memory hierarchy itself a fundamental part of AI system architecture.

If widely adopted, it could become an important building block for hyperscale AI servers, helping reduce memory bottlenecks while improving the economics and efficiency of large-scale inference infrastructure.