AMD and Meta Deepen AI Partnership: EPYC Venice, Helios and MI500

AMD and Meta Deepen AI Partnership: EPYC Venice, Helios and MI500

AMD and Meta are expanding their strategic collaboration across AI infrastructure, bringing together server CPUs, Instinct accelerators, rack-scale systems, networking, and software. The partnership now spans multiple generations of hardware, from EPYC processors already deployed across Meta’s infrastructure to upcoming Venice CPUs, custom MI450 accelerators, and future MI500 platforms.

In an announcement on October 27, 2026, AMD confirmed that Meta has deployed millions of EPYC processors across multiple generations and is a lead customer for the sixth-generation EPYC family, codenamed Venice. AMD also confirmed that initial Helios rack-scale systems have been installed and are being tested at Meta.

The collaboration extends beyond hardware procurement. AMD and Meta are jointly optimizing software, kernels, model architectures, and inference workflows to improve performance on AMD Instinct GPUs. These efforts have already produced measurable gains in recommendation-model training and Meta’s Muse Spark Open inference workloads.

The partnership is strategically important for AMD. Rather than competing solely through individual GPU products, the company is positioning itself as an alternative provider of complete AI infrastructure, combining CPUs, accelerators, networking, rack-scale systems, and an increasingly mature software ecosystem.

🤝 AMD and Meta Expand Their Strategic Hardware Partnership

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AMD’s relationship with Meta has developed over multiple generations of server processors and AI accelerators. The October 2026 announcement highlights how that relationship is evolving from component procurement into broader hardware and software co-development.

According to AMD, its technology already supports Meta’s infrastructure across several layers:

• EPYC CPUs: Millions of processors deployed across multiple generations, supporting infrastructure behind Meta’s Muse AI agent.
• Instinct GPUs: Production deployments supporting AI training, ranking, and recommendation workloads.
• Pensando networking: Networking technologies integrated into AMD’s broader AI infrastructure portfolio.
• ROCm software: The GPU software stack used to develop, optimize, and deploy AI workloads.
• Helios systems: Rack-scale infrastructure combining CPUs, GPUs, networking, and software.

Meta is not simply purchasing standard processors and accelerators. It is participating in the definition of future AMD products, aligning silicon and system roadmaps with its own AI workloads.

Venice: Meta becomes a lead customer for sixth-generation EPYC

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One of the most important announcements concerns AMD’s sixth-generation EPYC server processors, codenamed Venice.

Meta has become a lead customer for the new EPYC generation, building on its large installed base of previous-generation processors. This gives AMD a major hyperscale deployment partner for a new server CPU platform.

The role of CPUs in AI infrastructure is sometimes overlooked because GPUs receive most of the attention. However, CPUs remain essential for coordinating accelerator workloads, managing data pipelines, executing services, handling storage and networking operations, and orchestrating distributed infrastructure.

At Meta’s scale, these tasks require enormous amounts of general-purpose compute capacity.

The companies are also collaborating on future EPYC generations, including Verano. AMD describes Verano as a next-generation processor with workload-specific optimizations intended to improve performance per dollar and per watt.

The collaboration could allow AMD to tune future server processors more closely around the requirements of agentic AI infrastructure, where CPUs execute and coordinate many of the tasks surrounding model inference.

EPYC processors power Meta’s Muse AI infrastructure

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AMD confirmed that EPYC processors support the dedicated computing environments behind Meta’s Muse personal AI agent.

This is an important example of the relationship between server CPUs and AI accelerators. Although GPUs perform much of the neural-network computation, an agentic AI service also needs infrastructure for request handling, workflow coordination, tool execution, data access, and other application-level operations.

These supporting tasks can generate substantial CPU workloads, particularly when an AI service handles large numbers of concurrent users and multi-stage agent interactions.

As Meta expands its AI services, the need for efficient server CPU infrastructure will grow alongside accelerator demand.

🏢 Helios: AMD Moves From Individual Chips to Rack-Scale AI Systems

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The other major development is the deployment of AMD’s Helios rack-scale AI platform at Meta.

Unlike a conventional server deployment assembled around individual accelerator cards, Helios is designed as an integrated infrastructure platform. It combines multiple AMD technologies into a coordinated system intended for large-scale AI training and inference.

The architecture brings together:

This approach reflects an important shift in AI infrastructure design. As models become larger and clusters grow, individual accelerator specifications are no longer sufficient to determine system performance.

Memory capacity, accelerator interconnects, networking, power delivery, cooling, software scheduling, and system-level integration all influence how much useful work a rack can deliver.

For additional background, see KAD’s technical overview of the AMD Helios AI rack architecture.

Initial Helios systems are installed and undergoing testing

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AMD confirmed on October 27 that initial Helios rack-scale solutions have been installed and are being tested by Meta, ahead of broader deployment.

This distinction is important. The announcement establishes that Helios has moved into Meta’s infrastructure, but it does not mean the entire planned multi-gigawatt deployment is already operational.

The initial systems provide an opportunity to validate the integrated platform under Meta’s workloads before scaling deployment.

For AMD, this is a significant milestone. Successfully delivering rack-scale systems to a hyperscale customer requires more than producing high-performance GPUs. The complete system must work reliably across compute, networking, software, and operational infrastructure.

🚀 The 6-Gigawatt Instinct GPU Agreement and MI450 Deployment

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The expanded partnership builds on a major agreement announced on February 24, 2026, under which Meta agreed to deploy up to 6 gigawatts of AMD Instinct GPUs across multiple product generations.

The agreement is designed to support Meta’s next generation of AI infrastructure and aligns the companies’ roadmaps across processors, accelerators, systems, and software.

The initial deployment phase covers approximately 1 gigawatt of accelerator infrastructure.

Custom MI450 GPUs for Meta

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The initial phase is based on a custom AMD Instinct GPU built around the MI450 architecture and optimized for Meta’s workloads.

The planned system configuration combines:

• Custom Instinct MI450-based accelerators.
• Sixth-generation EPYC Venice CPUs.
• AMD Helios rack-scale infrastructure.
• AMD ROCm software.
• Integrated networking and system components.

Shipments supporting the first gigawatt deployment were originally scheduled to begin in the second half of 2026.

Meta was also an early definition customer for the MI450 architecture, meaning its workload requirements helped inform the product’s development. This goes beyond selecting an existing GPU configuration from AMD’s portfolio.

The custom approach gives AMD an opportunity to optimize the accelerator and system design around Meta’s specific requirements, potentially improving performance, efficiency, and infrastructure utilization.

However, the 6-GW figure represents the scale of the multi-year agreement, not a statement that all GPUs have already been delivered or installed.

Future MI500 collaboration

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The October 27 announcement also confirmed that the partnership is informing AMD’s future platforms, including the Instinct MI500 series and next-generation rack-scale systems.

This is an important part of the agreement’s long-term value. Meta can participate in future product planning while AMD gains access to detailed workload requirements from one of the world’s largest AI infrastructure operators.

The companies have not disclosed a complete MI500 deployment configuration or a specific Meta purchase volume for that generation. For now, MI500 should be understood as part of their future roadmap alignment rather than a confirmed production deployment.

For further details about AMD’s processor and accelerator roadmap, see KAD’s coverage of AMD Advancing AI 2026, including Venice, MI455X, and Helios.

🧠 Software Co-Optimization: Hardware Alone Is Not Enough

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A major part of the AMD-Meta partnership involves software engineering.

Meta operates a heterogeneous AI infrastructure fleet incorporating NVIDIA GPUs, AMD GPUs, and its own MTIA accelerators. This strategy helps the company diversify its compute supply, reduce dependence on a single vendor, and select hardware according to workload requirements.

However, moving AI workloads between accelerator platforms is not as simple as recompiling existing code.

Models originally optimized for NVIDIA GPUs may depend on CUDA-specific kernels, execution assumptions, memory behavior, and scheduling strategies. AMD GPUs use a different architecture and software stack, so a direct port may execute correctly without delivering competitive performance.

Meta’s engineering work demonstrates why hardware-model co-design and low-level software optimization are necessary when introducing alternative accelerators at hyperscale.

Three optimization strategies

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Meta’s collaboration with AMD highlights three important techniques for extracting more performance from Instinct GPUs.

1. Hardware-model co-design

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The first strategy is to adapt model structures and training configurations to the hardware rather than directly copying an existing model implementation.

A clear example is the memory capacity of the Instinct MI350X.

The MI350X provides 288GB of HBM3E memory, compared with 180GB on the NVIDIA B200 configuration used in Meta’s comparison. This gives the AMD accelerator approximately 1.6 times the HBM capacity.

Meta uses this additional capacity to explore larger per-GPU batch sizes, reduce activation checkpointing, and adjust data or model parallelism.

The larger memory pool can also support longer input sequences, wider hidden dimensions, and expanded embedding tables in recommendation models.

The lesson is that accelerator performance should be evaluated in the context of the model architecture and its memory requirements, rather than relying exclusively on peak compute throughput.

2. Zero-warmup kernel selection

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The second strategy involves selecting efficient GPU kernels without repeatedly executing workloads during a conventional warmup and autotuning process.

Meta developed an analytical performance-model approach that predicts suitable kernel configurations for different data types and matrix shapes.

This is especially useful in recommendation systems, where production workloads often involve irregular matrix dimensions and diverse computational patterns.

Instead of exhaustively benchmarking every possible kernel configuration, the performance model can estimate which implementation is likely to perform best.

The resulting approach simplifies tuning and reduces the engineering overhead associated with supporting different model configurations.

3. Agent-assisted CUDA migration

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The third strategy uses AI-assisted engineering workflows to reduce the effort required to migrate software from the CUDA ecosystem to AMD’s ROCm platform.

The process goes beyond automated source-code translation. Agent workflows can help developers identify hardware-specific bottlenecks, adjust kernel configurations, apply microarchitecture-aware optimizations, and generate custom compatibility layers when an equivalent library is unavailable.

This is particularly useful because AMD and NVIDIA GPUs have architectural differences that can prevent a directly translated kernel from achieving optimal performance.

For example, NVIDIA CUDA uses 32-thread warps, while AMD GPUs use 64-thread wavefronts. Software that assumes one execution model may need additional tuning to perform efficiently on the other.

Up to 1.5x improvement in training throughput

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Combining hardware-model co-design, analytical kernel selection, and agent-assisted migration produced substantial gains.

In Meta’s recommendation-model training work, the optimized AMD implementation achieved up to 1.5x end-to-end training throughput compared with the direct-port baseline.

The comparison needs to be interpreted correctly: this is an improvement over a relatively unoptimized migration baseline, not a claim that AMD MI350X is 1.5 times faster than NVIDIA B200.

Meta’s research paper also reports that, across a representative group of production recommendation models, MI350X achieved a geometric-mean throughput of approximately 101% of its established B200 baseline after optimization.

That result is significant because the B200 baseline had already benefited from extensive platform-specific engineering.

The work demonstrates that AMD GPUs can become a practical production training option when model architecture, kernels, and software are optimized together.

Meta and AMD have also upstreamed relevant improvements to the open-source PyTorch, Triton, and ROCm ecosystems, potentially benefiting other developers working with AMD accelerators.

⚡ Muse Spark Open: AMD MI350X Delivers Major Inference Improvements

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Another important part of the collaboration is AMD’s support for Meta’s Muse model family.

AMD announced Day-0 support for Muse Spark Open on October 15, 2026, enabling the model to run on Instinct MI350X and MI355X GPUs through ROCm and vLLM.

Muse Spark Open is a large Mixture-of-Experts (MoE) model designed for multimodal and agentic workloads, including long-running coding tasks, multi-file refactoring, and extended debugging.

Its reported model configuration is substantial:

The distinction between total and active parameters is important. Although the model contains 816 billion parameters, its sparse MoE architecture activates approximately 42 billion parameters for each token.

This reduces the computation required per token compared with activating the entire model, although the complete model weights still create substantial memory requirements.

Single-node MI350X deployment

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AMD demonstrated Muse Spark Open running on one node equipped with eight Instinct MI350X GPUs.

Each MI350X provides 288GB of HBM3E memory and up to 8TB/s of memory bandwidth. The eight accelerators operate together using tensor parallelism.

The software stack includes:

• ROCm 7.2.
• vLLM for model serving.
• AMD AITER kernels for attention, MoE computation, and communication.
• CUDA Graph capture for decode-step execution.
• BF16, MXFP4, and FP8 model variants.

Although Muse Spark Open supports a model-level context window of up to one million tokens, benchmark results must be interpreted according to the actual serving configuration. AMD’s published deployment recipe, for example, specifies a 32,768-token maximum model length for its documented configuration.

This is an important distinction when comparing headline model specifications with practical inference measurements.

📈 Decode Optimization: Up to 1,180 Tokens per Second

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AMD’s published results show substantial improvements after optimizing the decode pipeline.

The work combines fused attention and MoE operations, AITER paged attention, more efficient routing, and a reduction in kernel-launch overhead.

For the MXFP4 model configuration, the reported output throughput improved as follows:

At four concurrent requests, the optimized implementation increases throughput by approximately 70%.

At 32 concurrent requests, throughput rises from 719 to 1,180 tokens per second, an improvement of approximately 64%.

These gains demonstrate the importance of reducing software overhead and improving coordination between attention and expert-processing operations.

Expert parallelism improves high-concurrency performance

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AMD and Meta also evaluated expert parallelism with 32 of the model’s 256 experts assigned to each GPU.

This configuration improves how MoE computation is distributed across the accelerator cluster.

Across concurrency levels of 32 to 128 requests, the optimization delivered:

• 7%–20% higher throughput in MXFP4 mode.
• Approximately 24% lower time to first token (TTFT).
• Up to 2,197 tokens per second at 128 concurrent requests.

TTFT is especially important for interactive AI applications because it measures how long a user waits before receiving the first generated token.

Reducing TTFT can make an AI service feel more responsive, even when the total generation workload remains substantial.

Fused MoE routing optimization

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Another optimization focuses on the routing table used by the MoE implementation.

For smaller decode batches, AMD’s tuned AITER fused-MoE table selects a one-stage MXFP4 assembly kernel that avoids an additional sorting operation.

Under a Tensor Parallelism 8 (TP8) configuration, single-request decode throughput increased from 98 to 114 tokens per second.

That represents a 16% improvement without requiring a change to the model’s application code.

DSpark speculative decoding

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AMD also evaluated DSpark speculative decoding, which uses a draft model to predict potential output tokens before the main model verifies them.

This can reduce the number of sequential decoding operations required by the target model.

With the tuned TP8 configuration, DSpark achieved:

The results show that speculative decoding can be especially valuable for low-concurrency workloads, although its relative advantage decreases as the number of concurrent requests increases.

Accuracy remains within the reported range

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Performance improvements are useful only if they do not introduce unacceptable model-quality degradation.

AMD reported that Muse Spark Open’s GSM8K evaluation accuracy remained between 94.4% and 95.5% across the tested MXFP4 configurations, including tensor parallelism, expert parallelism, fused routing, and DSpark.

This indicates that the measured throughput improvements did not produce a substantial accuracy loss in that particular evaluation.

The result should not be interpreted as a guarantee of identical quality across every model task or evaluation dataset. It demonstrates stability under the configurations and benchmark used in AMD’s published testing.

For the full implementation details and benchmark methodology, see AMD’s Day-0 Muse Spark Open optimization report.

🔄 Muse Glimmer Extends AMD Support Beyond the Data Center

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The collaboration also extends to Meta’s Muse Glimmer model.

While Muse Spark Open targets large-scale server inference, AMD confirmed that Muse Glimmer has been adapted for AMD Ryzen AI PCs and Radeon GPUs.

This expands the partnership beyond hyperscale infrastructure into local AI computing.

The distinction is strategically important. Data-center accelerators support large models and high-concurrency services, while client processors and GPUs can provide local inference capabilities for supported AI applications.

By supporting both categories, AMD can position its hardware across more of the AI computing stack:

• EPYC CPUs: Server infrastructure and AI service orchestration.
• Instinct GPUs: Large-scale training and inference.
• Ryzen AI processors: Local AI acceleration on PCs.
• Radeon GPUs: Additional client-side AI processing.
• ROCm: Software infrastructure for supported accelerator workloads.

This broader coverage gives developers more opportunities to deploy AI models across different hardware environments.

🏗️ Meta’s Heterogeneous Compute Strategy and AMD’s Opportunity

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Meta’s infrastructure strategy is not based on replacing every existing accelerator with one vendor’s hardware.

Instead, the company operates a heterogeneous fleet that includes NVIDIA GPUs, AMD Instinct GPUs, and its proprietary MTIA accelerators.

This approach has several advantages.

Cost optimization: Meta can select hardware according to workload economics instead of relying on one accelerator platform for every task.

Supply-chain resilience: Multiple suppliers reduce exposure to shortages or procurement constraints affecting a single vendor.

Workload specialization: Different accelerators can be matched to different model architectures, training requirements, and inference services.

Negotiating flexibility: A credible alternative platform gives Meta more options when planning future infrastructure purchases.

The strategy also creates opportunities for AMD. By investing in software compatibility and working directly with Meta’s engineering teams, AMD can reduce the practical barriers that have historically made CUDA-based infrastructure difficult to migrate.

The production-scale recommendation-model results are particularly important because they demonstrate that AMD’s role can extend beyond selected inference workloads into more demanding training applications.

Why software co-engineering matters to AMD

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The GPU market is not determined by hardware specifications alone.

NVIDIA benefits from a mature software ecosystem, established developer workflows, optimized libraries, and years of application-specific engineering.

AMD’s ROCm ecosystem has improved, but hyperscale deployments require extensive validation and optimization across models, kernels, compilers, and distributed communication systems.

Working with Meta provides AMD with a major real-world engineering partner. Improvements developed for Meta’s workloads can also flow into open-source projects such as PyTorch and Triton, helping other organizations adopt AMD accelerators.

This creates a feedback loop: larger deployments generate more engineering experience, software improvements make additional deployments easier, and a broader production base strengthens the platform.

🔮 Outlook: AMD Is Building a Full-Stack Alternative for AI Infrastructure

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The expanded AMD-Meta partnership represents a significant milestone in AMD’s effort to establish a larger position in hyperscale AI infrastructure.

Meta has already deployed millions of EPYC processors and is a lead customer for sixth-generation Venice CPUs. The initial Helios racks are installed and undergoing testing, while the custom MI450-based GPU deployment is part of a broader multi-generation agreement targeting up to 6 gigawatts of accelerator infrastructure.

The collaboration also extends into future products, including Verano EPYC processors, Instinct MI500 accelerators, and next-generation rack-scale systems.

Just as importantly, the software work is producing measurable results. Meta’s recommendation-model engineering achieved up to 1.5x training throughput compared with a direct-migration baseline, while Muse Spark Open demonstrated substantial inference improvements on eight-GPU MI350X systems.

These results do not mean AMD has displaced NVIDIA across Meta’s infrastructure. Meta’s heterogeneous strategy explicitly retains multiple accelerator platforms, and performance depends on the workload and optimization effort. However, they demonstrate that AMD can serve as a viable production compute platform for increasingly demanding AI applications.

For AMD, the opportunity is larger than selling another generation of GPUs. By combining EPYC CPUs, Instinct accelerators, Pensando networking, Helios systems, and ROCm software, the company is attempting to compete at the level of complete AI infrastructure.

The next major test will be scaling the custom MI450 deployment and translating the current software and hardware collaboration into sustained production performance. If AMD can deliver on those goals, Meta could become one of the most important reference customers for its next generation of data-center CPUs, accelerators, and rack-scale systems.