Skip to main content

Montage Technology CXL 3.2 MXC Enters Samsung and SK Hynix

·2564 words·13 mins
Montage Technology CXL CXL 3.2 MXC PCIe 6.x PCIe Retimer Memory Pooling AI Infrastructure Semiconductor
Table of Contents

Montage Technology CXL 3.2 MXC Enters Samsung and SK Hynix

Montage Technology is accelerating its expansion into next-generation server memory and high-speed interconnect technologies. The company’s CXL 3.2 MXC chip has entered trial production and has reportedly been integrated into next-generation CXL products from major memory module manufacturers, including Samsung and SK Hynix.

The milestone arrives as Compute Express Link (CXL) transitions from early platform validation toward broader commercial deployment. Montage’s CXL 3.2 MXC supports CXL data rates of up to 64 GT/s and DDR data rates of up to 8000 MT/s, targeting memory expansion, memory pooling, and high-capacity memory architectures for data centers and AI servers.

At the same time, Montage is expanding its broader interconnect portfolio across PCIe Retimers, PCIe Switches, Ethernet PHY Retimers, memory-interface chips, and clocking solutions. Together, these products position the company across several critical connectivity layers of next-generation computing infrastructure.

πŸš€ CXL 3.2 MXC Reaches Trial Production
#

CXL 3.2 MXC Targets Next-Generation Memory Architectures
#

Montage Technology disclosed in an investor relations activity record that it took the lead in trial-producing its CXL 3.2 MXC chip in July 2026.

The device supports CXL data rates of up to 64 GT/s and DDR data rates of up to 8000 MT/s, providing the bandwidth required by increasingly demanding server and AI memory architectures.

Specification CXL 3.2 MXC
CXL Version CXL 3.2
CXL Data Rate Up to 64 GT/s
DDR Data Rate Up to 8000 MT/s
Primary Function Memory Expansion and Pooling
Target Applications Data Centers and AI Servers

Montage stated that the chip has already been designed into next-generation CXL products from major memory module manufacturers, including Samsung and SK Hynix.

This customer adoption is strategically significant because MXC devices occupy an important position between CXL host interfaces and DDR memory resources. As CXL architectures become more sophisticated, specialized controllers and multiplexing components can become essential building blocks for scalable memory systems.

PCIe 6.x/CXL 3.x Retimer Advances Toward Production
#

Montage is also making progress on its next-generation PCIe Retimer roadmap.

The company’s PCIe 6.x/CXL 3.x Retimer completed mass-production-version tape-out during the first half of 2026 and is currently undergoing customer testing and validation.

The product was also added to the PCI-SIG Integrators List, representing an important ecosystem qualification milestone.

Montage’s current PCIe Retimer shipments remain dominated by Gen 5 products, with related shipments increasing year over year during the first half of 2026.

The company is already looking beyond PCIe 6.x. Development of PCIe 7.0 Retimer technology is underway, with engineering-sample tape-out planned within 2026.

Industry expectations indicate that standard server CPU platforms supporting PCIe 6.x Retimers could enter mass production and shipment in 2027. This could create a significant commercial opportunity for Montage’s PCIe 6.x and CXL-related products.

πŸ“ˆ Interconnect Revenue Continues to Accelerate
#

New Products Drive Faster Growth
#

Montage Technology’s financial performance demonstrates the increasing contribution from its interconnect portfolio.

During the first half of 2026, the company generated approximately RMB 3.335 billion in revenue, representing year-over-year growth of 26.7%.

The interconnect chip product line generated approximately RMB 3.111 billion, up 26.4% year over year.

Four newer interconnect productsβ€”MRCD/MDB, PCIe Retimer, CKD, and CXL MXCβ€”generated combined revenue of approximately RMB 538 million. This represented an 80.7% year-over-year increase.

R&D investment also remained high.

Montage Technology’s R&D expenditure reached approximately RMB 453 million during the first half of 2026, an increase of nearly 27% year over year and equivalent to approximately 13.6% of total revenue.

The combination of high R&D intensity and rapidly growing revenue from newer interconnect products indicates that Montage is building a broader connectivity platform rather than relying on a single product category.

Product Portfolio Is Expanding Across Multiple Interfaces
#

Montage’s current development roadmap covers several critical technologies:

Product 2026 Status Primary Application
CXL 3.2 MXC Trial production CXL memory expansion and pooling
PCIe Gen 5 Retimer Commercial shipments Server and data-center connectivity
PCIe 6.x/CXL 3.x Retimer Customer validation Next-generation server platforms
PCIe 7.0 Retimer Engineering development Future high-speed platforms
PCIe Switch Engineering development PCIe fabric and system expansion
Ethernet PHY Retimer Engineering development AI server-to-switch connectivity
MRCD/MDB Commercial shipments Server memory systems
CKD Commercial shipments High-speed memory interfaces
Clock Generator Mass production Servers, eSSDs, and industrial systems
Clock Buffer Mass production Data centers and industrial control
RTC Engineering development Precision timing

This diversification gives Montage multiple entry points into increasingly bandwidth-intensive computing systems.

πŸ”— CXL Moves Toward Large-Scale Commercial Deployment
#

2026 Could Mark the Beginning of Broader Adoption
#

The semiconductor industry is increasingly focused on transitioning CXL from a platform technology under evaluation into a commercially deployable memory architecture.

Cloud service providers (CSPs) are actively deploying CXL-related products, while server CPU vendors continue integrating CXL capabilities into their platform roadmaps.

Industry analysis generally views 2026 as an important starting point for large-scale CXL deployment, with 2027 potentially becoming a major commercialization year.

As server CPU platforms supporting CXL 3.0 and later standards reach mass production, more sophisticated memory pooling and memory-sharing architectures can become practical at scale.

CXL changes the traditional relationship between compute and memory by allowing memory resources to be accessed through a standardized high-speed interconnect rather than requiring all capacity to remain directly attached to a processor.

This enables architectures in which memory can be expanded, pooled, shared, or dynamically allocated according to workload requirements.

CXL Addresses the Economics of Memory Expansion
#

The technology becomes particularly attractive as DRAM prices remain elevated.

Traditional server memory expansion requires additional directly attached DRAM capacity. As memory requirements continue increasing, this approach can become expensive and inefficient.

CXL-based memory expansion introduces an alternative architecture in which additional memory resources can be connected through CXL devices.

This can potentially improve memory utilization while reducing the amount of expensive directly attached DRAM required for workloads that do not need the lowest possible memory latency.

CXL can also provide opportunities to reuse legacy memory.

In suitable system architectures, older DDR4 memory can potentially be incorporated into newer platforms through CXL-based memory expansion, improving the economic value of existing memory resources.

πŸ€– CXL Expands Into AI Memory Infrastructure
#

CXL Complements HBM in AI Systems
#

CXL is no longer limited to conventional CPU-centric server architectures.

Selected TPU and GPU platforms have begun supporting CXL, opening additional opportunities for memory expansion in AI infrastructure.

AI accelerators require enormous memory capacity and bandwidth, but not every workload requires all memory resources to remain directly attached to the accelerator.

CXL can provide additional high-capacity memory resources to CPUs, GPUs, and TPUs through standardized high-speed links.

This is particularly relevant to large language model (LLM) inference.

Ultra-long context windows, static knowledge bases, retrieval data, and other large datasets can require more memory capacity than can be economically provided through accelerator-attached memory alone.

CXL can therefore complement high-bandwidth memory rather than directly replacing it.

A simplified architecture can be represented as:

                    AI / Server Platform
                            |
              +-------------+-------------+
              |                           |
          CPU / Host                 GPU / TPU
              |                           |
              +-------------+-------------+
                            |
                        CXL Fabric
                            |
              +-------------+-------------+
              |                           |
        CXL Memory Device            Memory Pool
              |                           |
          DDR DRAM                   DDR DRAM

This architecture separates compute-local memory from larger shared or pooled memory resources.

HBM can continue serving bandwidth-intensive accelerator workloads, while CXL-attached memory can provide additional capacity for workloads where capacity, flexibility, and cost efficiency are more important than absolute local-memory latency.

Memory Pooling Could Become a Key CXL Workload
#

Memory pooling is one of the most significant long-term applications for CXL.

Instead of allocating a fixed amount of memory to every compute node, a CXL-enabled infrastructure can potentially maintain shared pools of memory that are allocated according to workload demand.

For cloud and AI operators, this can improve resource utilization.

A workload requiring additional memory capacity could potentially access pooled resources without requiring the physical installation of additional local DRAM on the compute node.

This is particularly attractive in environments where workloads vary significantly in memory requirements.

🧩 Montage Technology Builds Two Major CXL Advantages
#

First-Mover Advantage in CXL MXC
#

Montage’s first major advantage is its early entry into CXL MXC development.

The company trial-produced its CXL 3.2 MXC in July 2026 and successfully entered the next-generation CXL product ecosystem of major memory manufacturers, including Samsung and SK Hynix.

Early customer engagement is particularly valuable in CXL because interoperability and platform validation require coordination across multiple components.

MXC suppliers must work with memory manufacturers, server CPU vendors, platform developers, and system integrators to validate:

  • CXL protocol behavior
  • DDR compatibility
  • Signal integrity
  • Firmware interoperability
  • System-level performance
  • Reliability and qualification

Entering these development cycles early can allow a semiconductor supplier to establish technical relationships before CXL reaches full commercial scale.

Deep Customer Relationships Create an Ecosystem Barrier
#

Montage also emphasizes close collaboration with customers during early-stage R&D.

Rather than entering the market only after specifications have been finalized, the company participates in customer development and validation cycles.

This creates deeper integration between the chip supplier and its customers.

For high-speed interconnect products, competitive differentiation depends on more than raw semiconductor specifications.

Signal integrity, firmware compatibility, interoperability, reliability, validation, and system-level optimization all influence eventual adoption.

These factors can create meaningful barriers for competitors attempting to enter the market later.

πŸ’Ύ Memory OEMs Open the Door to Third-Party MXC Suppliers
#

Another important development in the CXL ecosystem is the increasing willingness of memory OEMs to source MXC chips from third-party suppliers instead of developing every component internally.

This trend could accelerate specialization across the CXL supply chain.

A vertically integrated approach gives memory manufacturers greater control over product optimization, but third-party suppliers can distribute development costs across multiple customers while potentially accelerating product development.

As CXL architectures become more complex, specialized semiconductor companies can therefore occupy an increasingly important position between memory manufacturers and server platforms.

For Montage Technology, this creates a potentially significant addressable market.

The company’s existing expertise in PCIe Retimers, memory-interface chips, clocking devices, and other high-speed connectivity technologies also provides complementary technical capabilities for CXL development.

If CXL memory pooling and expansion achieve broad commercial adoption, third-party MXC suppliers could capture an increasing share of the CXL value chain.

⚑ PCIe Switch Development Extends the Interconnect Roadmap
#

SerDes Expertise Supports PCIe Switch Development
#

Montage is expanding beyond Retimers into PCIe Switch technology.

The company has accumulated significant SerDes expertise and customer relationships through the successful commercialization of PCIe Retimers.

These capabilities provide a technical foundation for developing PCIe Switch products.

During the first half of 2026, Montage steadily advanced engineering development of its PCIe Switch chips and expects to complete engineering-sample tape-out within the year.

PCIe Switches can play an important role in systems requiring multiple high-speed PCIe endpoints to communicate through a shared fabric.

Potential applications include:

  • AI accelerator servers
  • High-performance computing
  • Storage systems
  • Network infrastructure
  • Composable server architectures
  • PCIe expansion platforms

Market Timing Will Be Critical
#

Technical capability alone will not determine the commercial success of PCIe Switch products.

Montage has indicated that future market-share gains will depend on three factors:

  1. Strong technology reserves
  2. Reliable product delivery and qualification
  3. Accurate market-entry timing

The timing issue is particularly important for rapidly evolving standards such as PCIe 6.0 and PCIe 7.0.

Entering too early can increase development and validation risks, while entering too late can allow competitors to establish customer relationships and ecosystem advantages.

🌐 Ethernet and Clocking Products Broaden the Portfolio
#

Ethernet PHY Retimer Targets AI Server Networks
#

Montage is also entering the Ethernet interconnect market.

The company’s first Ethernet product under development is an Ethernet PHY Retimer designed primarily to improve signal integrity and reliability across high-speed connections between AI servers and network switches.

Engineering-sample tape-out is planned for 2026.

The product can also benefit from Montage’s existing customer relationships in PCIe interconnect products.

The technical challenge is closely related to that of PCIe Retimers.

As Ethernet signaling rates increase, channel loss, jitter, crosstalk, and other signal-integrity issues become increasingly difficult to manage.

Retimers can restore signal quality and extend the practical reach of high-speed links, making them increasingly important in large AI clusters and data-center networks.

Clocking Becomes More Important as Bandwidth Increases
#

Montage’s clocking portfolio includes:

  • Clock generators
  • Clock buffers
  • Spread-spectrum oscillators
  • Differential oscillators with spread-spectrum functionality
  • High-precision RTC chips

The company plans to complete engineering-sample tape-out of its high-precision RTC products during the second half of 2026.

During the first half of 2026, major clock-chip shipments included clock generators and clock buffers used in eSSDs, data-center servers, and industrial-control systems.

Montage has already received mass-production orders for related clock products.

As system bandwidth increases, clock accuracy and synchronization become increasingly important because high-speed interfaces have tighter timing requirements.

This creates natural product adjacency between clocking, memory interfaces, PCIe, Ethernet, and CXL.

πŸ—οΈ Montage Builds a Broader Data-Center Connectivity Platform
#

Montage Technology’s roadmap now extends well beyond a single CXL product.

The company’s strategy is increasingly centered on becoming a supplier of high-speed connectivity and interface silicon for next-generation computing infrastructure.

Its major product categories form a relatively coherent technology stack:

                 Data Center / AI Infrastructure
                              |
          +-------------------+-------------------+
          |                   |                   |
       Compute             Memory              Network
          |                   |                   |
       CPU/GPU              DDR/HBM            Ethernet
          |                   |                   |
          +---------+---------+---------+---------+
                    |                   |
                  PCIe                CXL
                    |                   |
             +------+-----+       +-----+------+
             |            |       |            |
          Retimer       Switch    MXC      Memory Pool
             |
           SerDes
             |
       Signal Integrity
             |
          Clocking

The strategic significance of this portfolio is the increasing convergence of compute, memory, and networking.

AI servers are pushing PCIe, Ethernet, DDR, CXL, and clocking technologies toward higher data rates and increasingly demanding signal-integrity requirements.

As bandwidth scales, system designers increasingly require specialized semiconductor components between processors, accelerators, memory devices, storage, and network infrastructure.

Montage is positioning its products across several of these critical interfaces.

πŸ“Š CXL Could Become a Major Growth Driver
#

Montage Technology’s CXL 3.2 MXC milestone arrives at a potentially important transition point for the CXL ecosystem.

The company has progressed from product development to trial production and customer integration, while its broader PCIe Retimer portfolio continues moving toward next-generation server platforms.

The long-term opportunity ultimately depends on whether CXL achieves broad adoption across commercial servers and AI infrastructure.

If CXL 3.x becomes a standard building block for memory expansion and pooling, demand could emerge across several use cases:

CXL Application Potential Benefit
Memory Expansion Adds capacity without relying exclusively on local DRAM
Memory Pooling Improves utilization across multiple compute devices
Memory Sharing Enables flexible resource allocation
Legacy DRAM Reuse Extends the value of existing DDR memory
AI Inference Provides additional capacity for large-context workloads
Cloud Infrastructure Enables flexible memory provisioning
Composable Systems Separates compute and memory resources

The key commercial inflection point could arrive as CXL-capable server CPUs reach mass production and cloud operators move from evaluation to large-scale deployment.

For Montage Technology, the combination of CXL MXC, PCIe Retimers, PCIe Switches, Ethernet Retimers, memory-interface chips, and clocking products provides multiple opportunities to participate in this transition.

The company’s CXL 3.2 MXC integration with major memory manufacturers is therefore more than an isolated product milestone. It represents a step toward establishing a broader position in the evolving memory and interconnect architecture of AI servers and data centers.

As CXL moves toward commercial maturity, memory pooling, memory expansion, and heterogeneous memory architectures could become increasingly important to next-generation infrastructure.

If that transition materializes, Montage Technology’s early CXL positioning, high-speed SerDes expertise, and established customer relationships could provide a strong foundation for long-term growth in the CXL and data-center interconnect markets.

Related

Why CXL Is Losing the AI Accelerator Interconnect Race
·1341 words·7 mins
CXL AI Accelerators PCIe NVLink SerDes HBM AI Infrastructure Interconnects
ScaleFlux Launches PCIe Gen6 SSD and CXL 3.2 Controllers
·985 words·5 mins
ScaleFlux FMS 2026 PCIe Gen6 CXL 3.2 NVMe SSD Memory Controller AI Infrastructure Hyperscale
Marvell CXL Switch Enables 48TB AI Memory Pools
·2229 words·11 mins
Marvell CXL AI Infrastructure AI Memory PCIe 6.0 KV Cache Data Centers Hyperscalers